first commit

01_Halfadder/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

01_Halfadder/01_Halfadder.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

01_Halfadder/design.vhd

@@ -0,0 +1,19 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Entity HA
+entity halfadder is
+    port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+-- Architecture HA
+architecture behavior of halfadder is
+begin
+  -- HA is made out of 2 gates:
+    sum_o <= a_i xor b_i;
+    cy_o <= a_i and b_i;
+end behavior;

01_Halfadder/testbench.vhd

@@ -0,0 +1,38 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Entity TB
+entity testbench is
+-- empty
+end testbench;
+
+
+-- Architecture TB
+architecture tb of testbench is
+
+-- DUT component declaration
+    component halfadder is
+        port (a_i :   in std_logic;
+            b_i :   in std_logic;
+            sum_o : out std_logic;
+            cy_o :  out std_logic);
+    end component;
+
+-- declare signals
+    signal sig_a, sig_b, sig_sum, sig_cy: std_logic;
+
+begin
+
+  -- DUT instantiation and port mapping
+    DUT: halfadder port map(
+        a_i => sig_a,
+        b_i => sig_b,
+        sum_o => sig_sum,
+        cy_o => sig_cy);
+    
+  -- apply testpattern
+    sig_a <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
+    sig_b <= '0', '1' after 200 ns;
+    
+end tb;

01_Halfadder/vhdl_ls.toml

@@ -0,0 +1,12 @@
+# auto-generated
+[Libraries]
+work.files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end

02_Fulladder/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

02_Fulladder/02_Fulladder.vhdpproj

@@ -0,0 +1,9 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="fulladder.vhd" />
+    <File Include="halfadder.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

02_Fulladder/design.vhd

@@ -0,0 +1 @@
+-- empty: NOT EVEN library (otherwise compiler error)

02_Fulladder/fulladder.vhd

@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder is
+    port (afa_i :   in std_logic;
+        bfa_i :   in std_logic;
+        cinfa_i :   in std_logic;
+        sumfa_o : out std_logic;
+        coutfa_o :  out std_logic);
+end fulladder;
+
+architecture fa_behaviour of fulladder is
+
+-- Halfadder component
+    component halfadder is
+        port (a_i :   in std_logic;
+            b_i :   in std_logic;
+            sum_o : out std_logic;
+            cy_o :  out std_logic);
+    end component;
+
+    signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;
+
+begin
+
+-- Instances of two halfadders
+    HA1: halfadder port map(
+        a_i => afa_i,
+        b_i => bfa_i,
+        sum_o => sig_ha1e,
+        cy_o => sig_ha1c);
+    
+    HA2: halfadder port map(
+        a_i => sig_ha1e,
+        b_i => cinfa_i,
+        sum_o => sumfa_o,
+        cy_o => sig_ha2c);
+
+-- The OR gate
+    coutfa_o <= sig_ha1c OR sig_ha2c;
+    
+end fa_behaviour;

02_Fulladder/halfadder.vhd

@@ -0,0 +1,16 @@
+-- The halfadder design
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity halfadder is
+    port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+architecture behavior of halfadder is
+begin
+    sum_o <= a_i xor b_i;
+    cy_o <= a_i and b_i;
+end behavior;

02_Fulladder/testbench.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+  -- DUT components
+    component fulladder is
+        port (afa_i :   in std_logic;
+            bfa_i :   in std_logic;
+            cinfa_i :   in std_logic;
+            sumfa_o : out std_logic;
+            coutfa_o :  out std_logic);
+    end component;
+
+    signal sig_afa, sig_bfa, sig_cinfa, sig_sumfa, sig_coutfa: std_logic;
+
+begin
+
+    -- Connect DUTs
+    DUT_s: fulladder port map(
+        afa_i => sig_afa,
+        bfa_i => sig_bfa,
+        cinfa_i => sig_cinfa,
+        sumfa_o => sig_sumfa,
+        coutfa_o => sig_coutfa);
+
+
+    sig_afa <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns,'0' after 400 ns, '1' after 500 ns, '0' after 600 ns, '1' after 700 ns;
+    sig_bfa <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 600 ns;
+    sig_cinfa <= '0', '1' after 400 ns;
+end tb;

02_Fulladder/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

03_MUX_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

03_MUX_Example/03_MUX_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

03_MUX_Example/design.vhd

@@ -0,0 +1,20 @@
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity myMux is
+  port (sel :   in std_logic_vector(1 downto 0);
+        data1_i :   in std_logic_vector(2 downto 0);
+        data2_i : in std_logic_vector(2 downto 0);
+        outp : out std_logic_vector(2 downto 0) );
+end myMux;
+
+
+architecture behavior  of myMux is
+  
+begin
+  with sel select outp <= data1_i when "00",
+                          data2_i when "01",
+                          "010" when others;
+end behavior;

03_MUX_Example/testbench.vhd

@@ -0,0 +1,39 @@
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+-- DUT component declaration
+component myMux is
+port (sel :   in std_logic_vector(1 downto 0);
+        data1_i :   in std_logic_vector(2 downto 0);
+        data2_i : in std_logic_vector(2 downto 0);
+        outp : out std_logic_vector(2 downto 0) );
+end component;
+
+signal sig1, sig2 : std_logic;
+signal sig_sel : std_logic_vector(1 downto 0);
+signal sig_data1, sig_data2, sig_outp : std_logic_vector(2 downto 0);
+
+
+begin
+-- DUT instance
+DUT: myMux port map(
+     sel => sig_sel,
+     data1_i => sig_data1,
+     data2_i => sig_data2,
+     outp => sig_outp);
+     
+sig_data1 <= "111";
+sig_data2 <= "000";
+sig_sel <= (sig2,sig1);
+
+sig1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
+sig2 <= '0', '1' after 200 ns;
+
+end tb;

03_MUX_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

04_ClockGen_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

04_ClockGen_Example/04_ClockGen_Example.vhdpproj

@@ -0,0 +1,10 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkGen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

04_ClockGen_Example/clkGen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

04_ClockGen_Example/testbench.vhd

@@ -0,0 +1,23 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+
+begin  
+  DUT: clkGen port map(
+     clk => sig_clk
+  );
+ 
+    
+end tb;

04_ClockGen_Example/vhdl_ls.toml

@@ -0,0 +1,14 @@
+# auto-generated
+[Libraries]
+work.files = [
+	'clkGen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'clkGen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end

05_Fulladder_allVariants/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

05_Fulladder_allVariants/05_Fulladder_allVariants.vhdpproj

@@ -0,0 +1,11 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="fulladder_process.vhd" />
+    <File Include="fulladder_select.vhd" />
+    <File Include="fulladder_struct.vhd" />
+    <File Include="halfadder.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

05_Fulladder_allVariants/fulladder_process.vhd

@@ -0,0 +1,38 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_proc is
+  port (afa_proc_i :   in std_logic;
+        bfa_proc_i :   in std_logic;
+        cinfa_proc_i :   in std_logic;
+        sumfa_proc_o : out std_logic;
+        coutfa_proc_o :  out std_logic);
+end fulladder_proc;
+
+architecture beh of fulladder_proc is
+
+signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
+signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
+
+begin
+ sig_INPUTS <= (cinfa_proc_i,bfa_proc_i,afa_proc_i); 
+
+ table : process (sig_INPUTS)
+ begin
+ IF (sig_INPUTS = "000") then sig_OUTPUTS <= "00";
+ elsif (sig_INPUTS = "001") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "010") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "011") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "100") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "101") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "110") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "111") then sig_OUTPUTS <= "11";
+ else sig_OUTPUTS <= "XX"; end if;
+ 
+ end process table;
+ 
+                      
+ sumfa_proc_o <= sig_OUTPUTS(0);
+ coutfa_proc_o <= sig_OUTPUTS(1);
+end beh;

05_Fulladder_allVariants/fulladder_select.vhd

@@ -0,0 +1,34 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_sel is
+  port (afa_sel_i :   in std_logic;
+        bfa_sel_i :   in std_logic;
+        cinfa_sel_i :   in std_logic;
+        sumfa_sel_o : out std_logic;
+        coutfa_sel_o :  out std_logic);
+end fulladder_sel;
+
+architecture behavior of fulladder_sel is
+
+signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
+signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
+
+begin
+ sig_INPUTS <= (cinfa_sel_i,bfa_sel_i,afa_sel_i); 
+
+ with sig_INPUTS select	
+    sig_OUTPUTS   <=  "00" when "000",	
+                      "01" when "001",
+                      "01" when "010",	
+                      "10" when "011",
+                      "01" when "100",	
+                      "10" when "101",
+                      "10" when "110",	
+                      "11" when "111",
+                      "XX" when others;
+                      
+ sumfa_sel_o <= sig_OUTPUTS(0);
+ coutfa_sel_o <= sig_OUTPUTS(1);
+end behavior;

05_Fulladder_allVariants/fulladder_struct.vhd

@@ -0,0 +1,43 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_struct is
+  port (afa_s_i :   in std_logic;
+        bfa_s_i :   in std_logic;
+        cinfa_s_i :   in std_logic;
+        sumfa_s_o : out std_logic;
+        coutfa_s_o :  out std_logic);
+end fulladder_struct;
+
+architecture structural of fulladder_struct is
+
+-- Halfadder component
+component halfadder is
+port (a_i :   in std_logic;
+      b_i :   in std_logic;
+      sum_o : out std_logic;
+      cy_o :  out std_logic);
+end component;
+
+signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;
+
+begin
+
+-- Instances of two halfadders
+  HA1: halfadder port map(
+     a_i => afa_s_i,
+     b_i => bfa_s_i,
+     sum_o => sig_ha1e,
+     cy_o => sig_ha1c);
+     
+  HA2: halfadder port map(
+  	 a_i => sig_ha1e,
+     b_i => cinfa_s_i,
+     sum_o => sumfa_s_o,
+     cy_o => sig_ha2c);
+
+-- The OR gate 
+  coutfa_s_o <= sig_ha1c OR sig_ha2c;
+     
+end structural;

05_Fulladder_allVariants/halfadder.vhd

@@ -0,0 +1,16 @@
+-- The halfadder design
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity halfadder is
+  port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+architecture behavior of halfadder is
+begin
+  sum_o <= a_i xor b_i;
+  cy_o <= a_i and b_i;
+end behavior;

05_Fulladder_allVariants/testbench.vhd

@@ -0,0 +1,141 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+-- DUT components
+component fulladder_struct is
+  port (afa_s_i :   in std_logic;
+        bfa_s_i :   in std_logic;
+        cinfa_s_i :   in std_logic;
+        sumfa_s_o : out std_logic;
+        coutfa_s_o :  out std_logic);
+end component;
+
+component fulladder_sel is
+  port (afa_sel_i :   in std_logic;
+        bfa_sel_i :   in std_logic;
+        cinfa_sel_i :   in std_logic;
+        sumfa_sel_o : out std_logic;
+        coutfa_sel_o :  out std_logic);
+end component;
+
+component fulladder_proc is
+  port (afa_proc_i :   in std_logic;
+        bfa_proc_i :   in std_logic;
+        cinfa_proc_i :   in std_logic;
+        sumfa_proc_o : out std_logic;
+        coutfa_proc_o :  out std_logic);
+end component;
+
+
+
+signal sig_afa_s, sig_bfa_s, sig_cinfa_s, sig_sumfa_s, sig_coutfa_s: std_logic;
+signal sig_afa_sel, sig_bfa_sel, sig_cinfa_sel, sig_sumfa_sel, sig_coutfa_sel: std_logic;
+signal sig_afa_proc, sig_bfa_proc, sig_cinfa_proc, sig_sumfa_proc, sig_coutfa_proc: std_logic;
+
+begin
+
+  -- Connect DUTs
+  DUT_s: fulladder_struct port map(
+     afa_s_i => sig_afa_s,
+     bfa_s_i => sig_bfa_s,
+     cinfa_s_i => sig_cinfa_s,
+     sumfa_s_o => sig_sumfa_s,
+     coutfa_s_o => sig_coutfa_s);
+  
+   DUT_sel: fulladder_sel port map(
+     afa_sel_i => sig_afa_sel,
+     bfa_sel_i => sig_bfa_sel,
+     cinfa_sel_i => sig_cinfa_sel,
+     sumfa_sel_o => sig_sumfa_sel,
+     coutfa_sel_o => sig_coutfa_sel);
+     
+   DUT_proc: fulladder_proc port map(
+     afa_proc_i => sig_afa_proc,
+     bfa_proc_i => sig_bfa_proc,
+     cinfa_proc_i => sig_cinfa_proc,
+     sumfa_proc_o => sig_sumfa_proc,
+     coutfa_proc_o => sig_coutfa_proc);
+  
+  stim :process is
+  
+  begin
+  
+  	sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 000 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 000 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 001 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 001 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 010 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 010 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 011 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 011 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 100 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 100 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 101 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 101 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 110 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 110 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 111 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 111 NOK" severity failure;
+    
+    wait;
+    
+  end process stim;
+    
+    
+    
+  
+  
+end tb;

05_Fulladder_allVariants/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

06_VELS_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

06_VELS_Example/06_VELS_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

06_VELS_Example/design.vhd

@@ -0,0 +1,13 @@
+-- be aware of the correct order!
+-- EDA compiles from left to right
+
+-- 1) gate entities 
+-- 2) architectures for the gate entities
+-- 3) Package (must be done after 1, because otherwise componante is not known)
+-- 4) your entity
+-- 5) your architecture (needs to know all above)
+-- 6) Testbench Entity
+-- 7) Testbench Architecture (in same file as testbench entity)
+
+
+-- This example is related to the first VELS taks using packages (if there is no package, skip step 1-3)

06_VELS_Example/testbench.vhd

@@ -0,0 +1,74 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.std_artih.all;
+
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+  -- declare your DUT
+  component gates is
+      port(   A,B,C,D : in    std_logic;
+              O       : out   std_logic);
+  end component;
+
+
+  -- needed signals
+  signal sig_A, sig_B, sig_C, sig_D, sig_O: std_logic;
+
+  begin
+
+    -- Connect DUT with tb signals
+    DUT: gates port map(
+       A => sig_A,
+       B => sig_B,
+       C => sig_C,
+       D => sig_D,
+       O => sig_O);
+
+    -- define process for testing our DUT
+    gate_tester : process
+
+     -- define a procedure (Slides 07) that applys input vector, waits and than checks output
+      procedure check_sample(val_A, val_B, val_C, val_D, val_O : in std_logic) is
+      begin
+
+		-- apply signals to DUT inputs
+        sig_A <= val_A;
+        sig_B <= val_B;
+        sig_C <= val_C;
+        sig_D <= val_D;
+
+		-- wait (at least 1 delta cycle)
+        wait for 10 ns;
+
+		-- check output of DUT and report possible error message
+        assert (sig_O = val_O) report "Error for A= " 
+        & std_logic'image(val_A) & " B= "  
+        & std_logic'image(val_B) & " C= " 
+        & std_logic'image(val_C) & " D= " 
+        & std_logic'image(val_D) & ". Output is "
+        & std_logic'image(sig_O)  & " but should be " 
+        & std_logic'image(val_O)  & "."
+        severity failure; 
+
+      end procedure check_sample;
+
+    begin
+
+      -- now use procedure to check different combinations
+      -- change this according to your solution
+      -- (can also be done with loop, but we havn't learned that yet)
+      check_sample('0','0','0','0','1');
+      check_sample('0','0','0','1','0');
+      check_sample('1','1','1','1','1');
+
+	  -- wait forever to stop process
+      wait;
+
+    end process gate_tester;
+
+end tb;

06_VELS_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

07_DTime_GateDelay_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

07_DTime_GateDelay_Example/07_DTime_GateDelay_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

07_DTime_GateDelay_Example/design.vhd

@@ -0,0 +1,17 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity log is
+  port (inp :   in std_logic;
+        C :   out std_logic);
+end log;
+
+architecture behavior of log is
+signal A,B : std_logic;
+begin
+  A <= NOT inp after 1 ns;
+  B <= A NAND '1' after 1 ns;
+  C <= A AND B after 1 ns;
+end behavior;

07_DTime_GateDelay_Example/testbench.vhd

@@ -0,0 +1,25 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+
+component log is
+port (inp :   in std_logic;
+        C :   out std_logic);
+end component;
+signal inp_in, C_in : std_logic;
+
+begin  
+  DUT: log port map(
+     inp => inp_in,
+     C => C_in
+  );
+  inp_in <= '1', '0' after 10 ns, '1' after 20 ns;
+    
+end tb;

07_DTime_GateDelay_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

08_InfereredLatch_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

08_InfereredLatch_Example/08_InfereredLatch_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

08_InfereredLatch_Example/design.vhd

@@ -0,0 +1,21 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity InfLatch is 
+port ( D:in std_logic;
+       En:in std_logic;
+       Q:out std_logic);
+end InfLatch;
+
+architecture beh of InfLatch is
+begin
+
+p0: process (D,En)
+begin
+ if En= '1' then
+ Q <= D;
+ end if;
+end process p0;
+
+end beh;

08_InfereredLatch_Example/testbench.vhd

@@ -0,0 +1,46 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+
+component InfLatch is
+port ( D:in std_logic;
+       En:in std_logic;
+       Q:out std_logic);
+end component;
+
+signal sig_D, sig_En, sig_Q : std_logic;
+
+begin  
+  DUT: InfLatch port map(
+     D => sig_D,
+     En => sig_en,
+     Q => sig_Q
+  );
+  
+stim : process 
+begin 
+ sig_D <= '1';
+ sig_EN <= '0';
+ wait for 10 ns;
+ sig_En <= '1';
+ wait for 2 ns;
+ sig_D <= '0';
+ wait for 2 ns;
+ sig_D <= '1';
+ wait for 10 ns;
+ sig_En <= '0';
+ wait for 2 ns;
+ sig_D <= '0';
+ wait for 2 ns;
+ sig_D <= '1';
+ wait;
+end process stim;
+
+end tb;

08_InfereredLatch_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

09_DFF_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

09_DFF_Example/09_DFF_Example.vhdpproj

@@ -0,0 +1,8 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

09_DFF_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

09_DFF_Example/design.vhd

@@ -0,0 +1,24 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity myDFF is 
+port ( clk:in std_logic;
+       D:in std_logic;
+       reset:in std_logic;
+       Q:out std_logic);
+end myDFF;
+
+architecture beh of myDFF is
+begin
+
+DFF: process ( Clk, reset )
+begin
+ If reset ='1' then
+  Q <='0';
+ Elsif (Clk'event and Clk ='1') then
+  Q <= D ;
+ end if ;
+end process DFF;
+
+end beh;

09_DFF_Example/testbench.vhd

@@ -0,0 +1,60 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component myDFF is
+port ( clk:in std_logic;
+       D:in std_logic;
+       reset:in std_logic;
+       Q:out std_logic);
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_D, sig_clk, sig_Q, sig_reset : std_logic;
+
+begin  
+  DUT: myDFF port map(
+     clk => sig_clk,
+     D => sig_D,
+     reset => sig_reset,
+     Q => sig_Q
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+  
+res_stim : process 
+begin 
+ sig_reset <= '0';
+ wait for 2 ns;
+ sig_reset <= '1';
+ wait for 10 ns;
+ sig_reset <= '0';
+ wait for 20 ns;
+ sig_reset <= '1';
+ wait for 1 ns;
+ sig_reset <= '0';
+ wait;
+end process res_stim;
+
+d_stim : process
+begin
+ sig_D <= '0';
+ wait for 17 ns;
+ sig_D <= '1';
+ wait for 30 ns;
+ sig_D <= '0';
+ wait;
+end process d_stim;
+
+end tb;

09_DFF_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

10_LFSR_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

10_LFSR_Example/10_LFSR_Example.vhdpproj

@@ -0,0 +1,8 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

10_LFSR_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

10_LFSR_Example/design.vhd

@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity LFSR is
+    Port ( clk     : in  std_logic;
+           value32 : out  std_logic_vector (31 downto 0);
+           value16 : out  std_logic_vector (15 downto 0);
+           value8  : out  std_logic_vector ( 7 downto 0));
+end LFSR;
+
+architecture Behavioral of LFSR is
+signal rnd32 : std_logic_vector (31 downto 0) := (others=>'0');
+signal rnd16 : std_logic_vector (15 downto 0) := (others=>'0');
+signal rnd8  : std_logic_vector ( 7 downto 0) := (others=>'0');
+begin
+   process begin
+      wait until rising_edge(CLK);
+       -- 8Bit
+       rnd8(7 downto 1) <= rnd8(6 downto 0) ;
+       rnd8(0) <= not(rnd8(7) XOR rnd8(6) XOR rnd8(4));
+       -- 16Bit
+       rnd16(15 downto 1) <= rnd16(14 downto 0) ;
+       rnd16(0) <= not(rnd16(15) XOR rnd16(14) XOR rnd16(13) XOR rnd16(4));
+       -- 32 Bit
+       rnd32(31 downto 1) <= rnd32(30 downto 0) ;
+       rnd32(0) <= not(rnd32(31) XOR rnd32(22) XOR rnd32(2) XOR rnd32(1));
+   end process;
+   value32 <= rnd32;
+   value16 <= rnd16;
+   value8  <= rnd8;
+end Behavioral;

10_LFSR_Example/testbench.vhd

@@ -0,0 +1,40 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component LFSR is
+Port ( clk     : in  std_logic;
+       value32 : out  std_logic_vector (31 downto 0);
+       value16 : out  std_logic_vector (15 downto 0);
+       value8  : out  std_logic_vector ( 7 downto 0));
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal  sig_clk : std_logic;
+signal sig_r8 : std_logic_vector (7 downto 0);
+signal sig_r16 : std_logic_vector (15 downto 0);
+signal sig_r32 : std_logic_vector (31 downto 0);
+
+begin  
+  DUT: LFSR port map(
+     clk => sig_clk,
+     value32 => sig_r32,
+     value16 => sig_r16,
+     value8 => sig_r8
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+
+end tb;

10_LFSR_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

11_MinArith/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

11_MinArith/11_MinArith.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

11_MinArith/design.vhd

@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity minArith is
+  port (a_i :   in std_logic_vector (7 downto 0);
+        b_i :   in std_logic_vector (7 downto 0);
+        ssum_o : out std_logic_vector (7 downto 0);
+        sdiff_o :  out std_logic_vector (7 downto 0);
+        usum_o : out std_logic_vector (7 downto 0);
+        udiff_o :  out std_logic_vector (7 downto 0);
+        ainc_o :  out std_logic_vector (7 downto 0));
+end minArith;
+
+-- behavioral description of the halfadder given by two gates
+architecture behavior of minArith is
+begin
+  ssum_o  <= std_logic_vector(signed(a_i)   + signed(b_i));
+  sdiff_o <= std_logic_vector(signed(a_i)   - signed(b_i));
+  usum_o  <= std_logic_vector(unsigned(a_i) + unsigned(b_i));
+  udiff_o <= std_logic_vector(unsigned(a_i) - unsigned(b_i));
+  ainc_o  <= std_logic_vector(unsigned(a_i) + "00000001");
+  
+end behavior;

11_MinArith/testbench.vhd

@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+component minArith is
+port (a_i :   in std_logic_vector (7 downto 0);
+      b_i :   in std_logic_vector (7 downto 0);
+      ssum_o : out std_logic_vector (7 downto 0);
+      sdiff_o :  out std_logic_vector (7 downto 0);
+      usum_o : out std_logic_vector (7 downto 0);
+      udiff_o :  out std_logic_vector (7 downto 0);
+      ainc_o :  out std_logic_vector (7 downto 0));
+end component;
+
+
+signal sig_a, sig_b, sig_ssum, sig_sdiff, sig_usum, sig_udiff, sig_ainc : std_logic_vector(7 downto 0);
+
+begin
+
+  DUT: minArith port map(
+      a_i => sig_a,
+      b_i => sig_b,
+      ssum_o => sig_ssum,
+      sdiff_o => sig_sdiff,
+      usum_o => sig_usum,
+      udiff_o => sig_udiff,
+      ainc_o => sig_ainc );
+
+  
+  
+  sig_a <= "00000001", "00000010" after 100 ns, "00001010" after 200 ns;
+  sig_b <= "00000001", "00000011" after 100 ns, "00100010" after 200 ns;
+
+end tb;

11_MinArith/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

12_HA_with_assert_tb_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

12_HA_with_assert_tb_Example/12_HA_with_assert_tb_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

12_HA_with_assert_tb_Example/design.vhd

@@ -0,0 +1,18 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- entity of the halfadder
+-- 2 inputs, 2 outputs, both of type IEEE1164 std_logic
+entity halfadder is
+  port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+-- behavioral description of the halfadder given by two gates
+architecture behavior of halfadder is
+begin
+  sum_o <= a_i xor b_i;
+  cy_o <= a_i and b_i;
+end behavior;

12_HA_with_assert_tb_Example/testbench.vhd

@@ -0,0 +1,70 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- the entity of the testbench is empty, no connection to the outer world
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+-- DUT (device under test = halfadder) component declaration
+component halfadder is
+port (a_i :   in std_logic;
+      b_i :   in std_logic;
+      sum_o : out std_logic;
+      cy_o :  out std_logic);
+end component;
+
+-- signals for the testbench
+signal sig_a, sig_b, sig_sum_out, sig_cy_out: std_logic;
+
+begin
+
+  -- Connect DUT with tb signals
+  DUT: halfadder port map(
+     a_i => sig_a,
+     b_i => sig_b,
+     sum_o => sig_sum_out,
+     cy_o => sig_cy_out);
+  
+  -- Process for DUT Test
+  stimTest : process
+  
+   -- Procedure for applying an input vector
+   procedure applyTv(inputs : in std_logic_vector (1 downto 0)) is
+    begin
+    sig_a <= inputs(0);
+    sig_b <= inputs(1);
+    wait for 10 ns;
+   end procedure applyTv;
+   
+   -- Procedure for checking the outputs
+   procedure check(outputs : in std_logic_vector (1 downto 0)) is
+   begin
+    
+    assert (sig_sum_out = outputs(0))
+    report "Testpattern " & std_logic'image(sig_a) & " " & std_logic'image(sig_b) & " Error in sum_out got " & 		std_logic'image(sig_sum_out) & " expected " & std_logic'image(outputs(0)) severity error;
+    
+    assert (sig_cy_out = outputs(1))
+    report "Testpattern " & std_logic'image(sig_b) & " " & std_logic'image(sig_a) & " Error in cy_out got " & std_logic'image(sig_cy_out) & " expected " & std_logic'image(outputs(1)) severity error;
+   
+   end procedure check;
+
+
+
+  begin
+  
+   -- Let's apply different input vectors and check the output
+   applyTv("00");
+   check("00");
+   applyTv("01");
+   check("01");
+   applyTv("10");
+   check("01");
+   applyTv("11");
+   check("10");
+   wait;
+   
+  end process stimTest;
+
+end tb;

12_HA_with_assert_tb_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

13_procedure_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

13_procedure_Example/13_procedure_Example.vhdpproj

@@ -0,0 +1,7 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

13_procedure_Example/design.vhd

@@ -0,0 +1,14 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity MyDesign is
+  port (clk_i :   in std_logic;
+        data_i :   in std_logic);
+end MyDesign;
+
+
+architecture behavior of MyDesign is
+begin
+
+end behavior;

13_procedure_Example/testbench.vhd

@@ -0,0 +1,108 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+--use IEEE.std_artih.all;
+
+
+entity testbench is
+end testbench; 
+
+
+architecture tb of testbench is
+
+component MyDesign is
+port (clk_i :   in std_logic;
+      data_i :   in std_logic);
+end component;
+
+
+
+signal sig_data, sig_clk: std_logic;
+signal send_count : integer :=0;
+
+begin
+
+  -- Connect DUT with tb signals
+  DUT: MyDesign port map(
+     clk_i => sig_clk,
+     data_i => sig_data);
+     
+  stimTest : process
+  
+   procedure send(d0,d1,d2,d3 : in std_logic) is
+    begin
+    
+    if (send_count=0) then
+      assert ((d0='1') AND (d1='1') AND (d2='1') AND (d3='1')) report "error in first frame (d0,d1,d2,d3) is " 
+      & std_logic'image(d0)
+      & std_logic'image(d1)
+      & std_logic'image(d2)
+      & std_logic'image(d3)
+      severity error; 
+    end if;
+    
+    wait for 4 ms;
+    
+    sig_data <= '0';
+    sig_clk <= '1';
+    
+    for I in 0 to 3 loop
+		wait for 1 ms;
+        sig_clk <= NOT sig_clk;
+	end loop;
+    
+    sig_data <= d0;
+    sig_clk <= '1';
+    wait for 1 ms;
+    sig_clk <= '0';
+    wait for 1 ms;
+    
+    sig_data <= d1;
+    sig_clk <= '1';
+    wait for 1 ms;
+    sig_clk <= '0';
+    wait for 1 ms;
+    
+    sig_data <= d2;
+    sig_clk <= '1';
+    wait for 1 ms;
+    sig_clk <= '0';
+    wait for 1 ms;
+    
+    sig_data <= d3;
+    sig_clk <= '1';
+    wait for 1 ms;
+    sig_clk <= '0';
+    wait for 1 ms;
+    
+    sig_data <= '0';
+    sig_clk <= '1';
+    wait for 1 ms;
+    sig_clk <= '0';
+    wait for 1 ms;
+    
+    sig_data <= '1';
+    sig_clk <= '1';
+    wait for 1ms;
+    sig_clk <= '0';
+    
+    send_count <= send_count+1;
+
+   end procedure send;
+   
+   
+  begin
+  
+  sig_clk <= '0';
+  sig_data <= '1';
+  
+  send('1','0','1','0');
+  
+  wait for 10 ms;
+  
+  send('0','1','0','1');
+  
+   
+  wait;
+  end process stimTest;
+
+end tb;

13_procedure_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

14_FSM_Moore_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

14_FSM_Moore_Example/14_FSM_Moore_Example.vhdpproj

@@ -0,0 +1,8 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

14_FSM_Moore_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

14_FSM_Moore_Example/design.vhd

@@ -0,0 +1,81 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FSM is
+    port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           start : in  STD_LOGIC;
+           stop  : in  STD_LOGIC;
+           cout  : out  STD_LOGIC_VECTOR (2 downto 0));
+end FSM;
+
+architecture beh of FSM is
+
+type state_t is (cs_reset,cs_wait,cs_one,cs_two,cs_three,cs_four,cs_five);
+signal state, next_state : state_t := cs_reset;
+
+
+begin
+
+p_seq: process (clk,reset)
+begin
+ if reset ='1' then
+   state <= cs_reset;
+ elsif (Clk'event and Clk ='1') then
+   state   <= next_state;
+ end if;
+end process p_seq;
+
+p_comb: process (state,start,stop)
+begin
+ case state is
+         when cs_reset => next_state <= cs_wait;
+                          cout <= "XXX";
+                      
+         when cs_wait  => if (start='1' and stop='0') then
+                           next_state <= cs_one;
+                          else
+                           next_state <= cs_wait;
+                          end if;
+                          cout <= "000";
+        
+         when cs_one  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_two;
+                         end if;
+                         cout <= "001";
+                      
+
+         when cs_two  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_three;
+                         end if;
+                         cout <= "010";
+                         
+         when cs_three  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_four;
+                         end if;
+                         cout <= "011";
+                         
+         when cs_four  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_five;
+                         end if;
+                         cout <= "100";
+         
+         when cs_five  => next_state <= cs_wait;
+                          cout <= "101";
+                                               
+      end case;
+      
+end process p_comb;
+
+
+
+end beh;

14_FSM_Moore_Example/testbench.vhd

@@ -0,0 +1,45 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component FSM is
+port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           start : in  STD_LOGIC;
+           stop  : in  STD_LOGIC;
+           cout  : out  STD_LOGIC_VECTOR (2 downto 0));
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk, sig_reset, sig_start, sig_stop : std_logic;
+signal sig_cout : STD_LOGIC_VECTOR (2 downto 0);
+
+begin  
+  DUT: FSM port map(
+     clk => sig_clk,
+     reset => sig_reset,
+     start => sig_start,
+     stop => sig_stop,
+     cout => sig_cout
+   );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+  
+
+
+sig_start <= '0', '1' after 22 ns, '0' after 45 ns, '1' after 82 ns, '0' after 86 ns;
+
+sig_reset <='0','1' after 102 ns, '0' after 123 ns;
+sig_stop <= '0', '1' after 58 ns, '0' after 68 ns;
+end tb;

14_FSM_Moore_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

15_FSM_Mealy_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj

@@ -0,0 +1,9 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="fsm_syn.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

15_FSM_Mealy_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

15_FSM_Mealy_Example/fsm_syn.vhd

@@ -0,0 +1,79 @@
+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FSM_sync is
+    port ( clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out_sync  : out STD_LOGIC);
+end FSM_sync;
+
+architecture beh of FSM_sync is
+
+  type state_t is (S_start,S_direct,S_invert);
+
+  signal state : state_t := S_start;
+  signal next_state : state_t := S_start;
+
+  signal dbg_state: std_logic_vector(1 downto 0); -- just for  debugging (we can't see type state_t in the waveform viewer)
+
+  signal next_data_out : std_logic := '0';
+
+begin
+
+  p_seq: process (clk)
+  begin
+   if (clk'event and clk ='1') then
+     state   <= next_state;
+     data_out_sync <= next_data_out;
+   end if;
+  end process p_seq;
+
+
+  p_comb: process (state,data_in,direct,invert)
+  begin
+   case state is
+           when S_start => if direct AND NOT invert then
+                           next_data_out <= data_in;
+                           next_state <= S_direct;
+                         elsif  invert AND NOT direct then
+                           next_data_out <= not data_in;
+                           next_state <= S_invert;
+                         else
+                           next_data_out <= '0';
+                           next_state <= S_start;
+                         end if;
+
+           when S_direct  => if direct and not invert then
+                             next_state <= S_direct;
+                             next_data_out <= data_in;                   
+                           else
+                             next_state <= S_start;
+                             next_data_out <= '0';
+                         end if;
+
+           when S_invert => if invert and not direct then
+                             next_state <= S_invert;
+                             next_data_out <= not data_in;                   
+                           else
+                             next_state <= S_start;
+                             next_data_out <= '0';
+                         end if;
+        end case;
+
+  end process p_comb;
+
+  -- just for debugging, we transform the state (type state_t) to a 2bit vector, which we can see in the waveform viewer
+  dbg: process (state)
+  begin
+   case state is
+           when S_start => dbg_state <= "00";                   
+           when S_direct  => dbg_state <= "01";
+           when S_invert  => dbg_state <= "10";
+        end case;
+  end process dbg;
+
+
+end beh;

15_FSM_Mealy_Example/testbench.vhd

@@ -0,0 +1,60 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component FSM is
+port (  clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out : out STD_LOGIC);
+end component;
+
+component FSM_sync is
+port (  clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out_sync : out STD_LOGIC);
+end component;
+
+
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk, sig_din,sig_dout, sig_dout_sync, sig_direct, sig_invert : std_logic;
+
+
+begin  
+  DUT: FSM port map(
+     clk => sig_clk,
+     direct => sig_direct,
+     invert => sig_invert,
+     data_in => sig_din,
+     data_out => sig_dout
+   );
+   
+    DUT_sync: FSM_sync port map(
+     clk => sig_clk,
+     direct => sig_direct,
+     invert => sig_invert,
+     data_in => sig_din,
+     data_out_sync => sig_dout_sync
+   );
+   
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+sig_din <='0', '1' after 22 ns, '0' after 40 ns, '1' after 100 ns, '0' after 140 ns, '1' after 142 ns, '0' after 150 ns, '1' after 170 ns, '0' after 200 ns, '1' after 282 ns, '0' after 482 ns, '1' after 500 ns, '0' after 525 ns, '1' after 570 ns, '0' after 632ns, '1' after 750 ns;
+sig_direct<= '0',  '1' after 100 ns, '0' after 400 ns, '1' after 600 ns;
+sig_invert<= '0',  '1' after 350 ns, '0' after 650 ns, '1' after 700 ns;
+end tb;

15_FSM_Mealy_Example/vhdl_ls.toml

@@ -0,0 +1,8 @@
+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end

16_asyncROM_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

16_asyncROM_Example/16_asyncROM_Example.vhdpproj

@@ -0,0 +1,9 @@
+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

16_asyncROM_Example/design.vhd

@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_rom is
+    port
+    (
+        addr    : in std_logic_vector(3 downto 0);
+        q        : out std_logic_vector(4 downto 0)
+    );
+end single_port_rom;
+    
+architecture rtl of single_port_rom is
+
+    -- Build a 2-D array type for the ROM
+    subtype word_t is std_logic_vector(4 downto 0);
+    type memory_t is array(0 to 15) of word_t;
+        
+    constant romdata : memory_t := (
+     "10101",                            -- data for address 0
+     "11111",                            -- data for address 1
+     "10101",
+     "11110",
+     "10110",
+     "10101",
+     "11010",
+     "10010",
+     "10110",
+     "11101",
+     "10110",
+     "10111",
+     "00110",
+     "11101",
+     "10010",
+     "10110"                             -- data for address 15
+     );
+          
+begin
+        q <= romdata(to_integer(unsigned(addr)));
+        
+end rtl;

16_asyncROM_Example/testbench.vhd

@@ -0,0 +1,47 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_rom is
+port
+    (
+        addr    : in std_logic_vector(3 downto 0);
+        q        : out std_logic_vector(4 downto 0)
+    );
+end component;
+
+
+signal sig_addr : std_logic_vector(3 downto 0);
+signal sig_q : std_logic_vector(4 downto 0);
+
+
+begin  
+  DUT: single_port_rom port map(
+     addr => sig_addr,
+     q => sig_q
+  );
+  
+
+
+stim: process 
+begin
+sig_addr <= "0000";
+wait for 10 ns;
+sig_addr <= "0001";
+wait for 10 ns;
+sig_addr <= "0010";
+wait for 10 ns;
+sig_addr <= "0100";
+wait for 10 ns;
+sig_addr <= "1000";
+wait;
+end process stim;
+
+
+end tb;

16_asyncROM_Example/vhdl_ls.toml

@@ -0,0 +1,12 @@
+# auto-generated
+[Libraries]
+work.files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end

17_syncROM_Example/.gitignore

@@ -0,0 +1,40 @@
+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

17_syncROM_Example/17_syncROM_Example.vhdpproj

@@ -0,0 +1,10 @@
+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

17_syncROM_Example/clkgen.vhd

@@ -0,0 +1,24 @@
+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

17_syncROM_Example/design.vhd

@@ -0,0 +1,45 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_rom is
+    port
+    (
+        addr    : in std_logic_vector(15 downto 0);
+        clk        : in std_logic;
+        q        : out std_logic_vector(7 downto 0)
+    );
+end single_port_rom;
+    
+architecture rtl of single_port_rom is
+
+    -- Build a 2-D array type for the RoM
+    subtype word_t is std_logic_vector(7 downto 0);
+    type memory_t is array(0 to 5) of word_t;
+        
+    constant romdata : memory_t := (
+     X"FF",                            -- data for address 0 in HEX notation
+     X"A5",                            -- data for address 1 in HEX notation
+     X"AA",
+     X"B6",
+     X"5C",
+     X"23"
+     );
+     
+         
+begin
+    
+    process(clk)
+    variable addr_to_read : integer;
+    begin
+        if(rising_edge(clk)) then
+         addr_to_read := to_integer(unsigned(addr));
+         if addr_to_read <= 5 then
+          q <= romdata(addr_to_read);
+         else
+          q <= "XXXXXXXX";
+         end if;
+        end if;
+    end process;
+        
+end rtl;

17_syncROM_Example/testbench.vhd

@@ -0,0 +1,51 @@
+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_rom is
+port
+	(
+		addr	: in std_logic_vector(15 downto 0);
+		clk		: in std_logic;
+		q		: out std_logic_vector(7 downto 0)
+	);
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+signal sig_addr : std_logic_vector(15 downto 0);
+signal sig_q : std_logic_vector(7 downto 0);
+
+
+begin  
+  DUT: single_port_rom port map(
+     clk => sig_clk,
+     addr => sig_addr,
+     q => sig_q
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+stim: process 
+begin
+sig_addr <= "0000000000000000";
+wait for 12 ns;
+sig_addr <= "0000000000000001";
+wait for 12 ns;
+sig_addr <= std_logic_vector(to_unsigned(10,16));
+wait;
+end process stim;
+
+
+end tb;

17_syncROM_Example/vhdl_ls.toml

@@ -0,0 +1,14 @@
+# auto-generated
+[Libraries]
+work.files = [
+	'clkgen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'clkgen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end