39 lines
793 B
VHDL
39 lines
793 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- Entity TB
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entity testbench is
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-- empty
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end testbench;
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-- Architecture TB
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architecture tb of testbench is
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-- DUT component declaration
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component halfadder is
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port (a_i : in std_logic;
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b_i : in std_logic;
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sum_o : out std_logic;
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cy_o : out std_logic);
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end component;
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-- declare signals
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signal sig_a, sig_b, sig_sum, sig_cy: std_logic;
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begin
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-- DUT instantiation and port mapping
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DUT: halfadder port map(
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a_i => sig_a,
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b_i => sig_b,
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sum_o => sig_sum,
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cy_o => sig_cy);
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-- apply testpattern
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sig_a <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
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sig_b <= '0', '1' after 200 ns;
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end tb;
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