25 lines
407 B
VHDL
25 lines
407 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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-- empty
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end testbench;
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architecture tb of testbench is
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component log is
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port (inp : in std_logic;
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C : out std_logic);
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end component;
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signal inp_in, C_in : std_logic;
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begin
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DUT: log port map(
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inp => inp_in,
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C => C_in
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);
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inp_in <= '1', '0' after 10 ns, '1' after 20 ns;
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end tb; |