35 lines
924 B
VHDL
35 lines
924 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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-- empty
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end testbench;
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architecture tb of testbench is
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-- DUT components
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component fulladder is
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port (afa_i : in std_logic;
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bfa_i : in std_logic;
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cinfa_i : in std_logic;
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sumfa_o : out std_logic;
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coutfa_o : out std_logic);
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end component;
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signal sig_afa, sig_bfa, sig_cinfa, sig_sumfa, sig_coutfa: std_logic;
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begin
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-- Connect DUTs
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DUT_s: fulladder port map(
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afa_i => sig_afa,
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bfa_i => sig_bfa,
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cinfa_i => sig_cinfa,
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sumfa_o => sig_sumfa,
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coutfa_o => sig_coutfa);
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sig_afa <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns,'0' after 400 ns, '1' after 500 ns, '0' after 600 ns, '1' after 700 ns;
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sig_bfa <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 600 ns;
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sig_cinfa <= '0', '1' after 400 ns;
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end tb;
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