16 lines
337 B
VHDL
16 lines
337 B
VHDL
-- The halfadder design
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity halfadder is
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port (a_i : in std_logic;
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b_i : in std_logic;
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sum_o : out std_logic;
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cy_o : out std_logic);
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end halfadder;
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architecture behavior of halfadder is
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begin
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sum_o <= a_i xor b_i;
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cy_o <= a_i and b_i;
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end behavior; |