38 lines
1.1 KiB
VHDL
38 lines
1.1 KiB
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fulladder_proc is
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port (afa_proc_i : in std_logic;
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bfa_proc_i : in std_logic;
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cinfa_proc_i : in std_logic;
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sumfa_proc_o : out std_logic;
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coutfa_proc_o : out std_logic);
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end fulladder_proc;
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architecture beh of fulladder_proc is
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signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
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signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
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begin
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sig_INPUTS <= (cinfa_proc_i,bfa_proc_i,afa_proc_i);
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table : process (sig_INPUTS)
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begin
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IF (sig_INPUTS = "000") then sig_OUTPUTS <= "00";
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elsif (sig_INPUTS = "001") then sig_OUTPUTS <= "01";
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elsif (sig_INPUTS = "010") then sig_OUTPUTS <= "01";
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elsif (sig_INPUTS = "011") then sig_OUTPUTS <= "10";
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elsif (sig_INPUTS = "100") then sig_OUTPUTS <= "01";
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elsif (sig_INPUTS = "101") then sig_OUTPUTS <= "10";
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elsif (sig_INPUTS = "110") then sig_OUTPUTS <= "10";
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elsif (sig_INPUTS = "111") then sig_OUTPUTS <= "11";
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else sig_OUTPUTS <= "XX"; end if;
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end process table;
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sumfa_proc_o <= sig_OUTPUTS(0);
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coutfa_proc_o <= sig_OUTPUTS(1);
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end beh; |