45 lines
945 B
VHDL
45 lines
945 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component FSM is
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port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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start : in STD_LOGIC;
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stop : in STD_LOGIC;
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cout : out STD_LOGIC_VECTOR (2 downto 0));
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk, sig_reset, sig_start, sig_stop : std_logic;
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signal sig_cout : STD_LOGIC_VECTOR (2 downto 0);
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begin
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DUT: FSM port map(
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clk => sig_clk,
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reset => sig_reset,
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start => sig_start,
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stop => sig_stop,
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cout => sig_cout
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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sig_start <= '0', '1' after 22 ns, '0' after 45 ns, '1' after 82 ns, '0' after 86 ns;
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sig_reset <='0','1' after 102 ns, '0' after 123 ns;
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sig_stop <= '0', '1' after 58 ns, '0' after 68 ns;
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end tb; |