TU-VHDL/17_syncROM_Example/vhdl_ls.toml
2025-02-10 20:28:13 +01:00

14 lines
189 B
TOML

# auto-generated
[Libraries]
work.files = [
'clkgen.vhd',
'design.vhd',
'testbench.vhd'
]
[libraries.work]
files = [
'clkgen.vhd',
'design.vhd',
'testbench.vhd'
]
# auto-generated-end