TU-VHDL/15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj
2025-02-10 20:28:13 +01:00

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<Project>
<ItemGroup>
<File Include="clkgen.vhd" />
<File Include="design.vhd" />
<File Include="fsm_syn.vhd" />
<File Include="testbench.vhd" />
</ItemGroup>
<PropertyGroup />
</Project>