60 lines
1.5 KiB
VHDL
60 lines
1.5 KiB
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component FSM is
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port ( clk : in STD_LOGIC;
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data_in : in STD_LOGIC;
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direct : in STD_LOGIC;
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invert : in STD_LOGIC;
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data_out : out STD_LOGIC);
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end component;
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component FSM_sync is
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port ( clk : in STD_LOGIC;
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data_in : in STD_LOGIC;
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direct : in STD_LOGIC;
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invert : in STD_LOGIC;
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data_out_sync : out STD_LOGIC);
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk, sig_din,sig_dout, sig_dout_sync, sig_direct, sig_invert : std_logic;
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begin
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DUT: FSM port map(
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clk => sig_clk,
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direct => sig_direct,
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invert => sig_invert,
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data_in => sig_din,
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data_out => sig_dout
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);
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DUT_sync: FSM_sync port map(
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clk => sig_clk,
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direct => sig_direct,
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invert => sig_invert,
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data_in => sig_din,
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data_out_sync => sig_dout_sync
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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sig_din <='0', '1' after 22 ns, '0' after 40 ns, '1' after 100 ns, '0' after 140 ns, '1' after 142 ns, '0' after 150 ns, '1' after 170 ns, '0' after 200 ns, '1' after 282 ns, '0' after 482 ns, '1' after 500 ns, '0' after 525 ns, '1' after 570 ns, '0' after 632ns, '1' after 750 ns;
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sig_direct<= '0', '1' after 100 ns, '0' after 400 ns, '1' after 600 ns;
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sig_invert<= '0', '1' after 350 ns, '0' after 650 ns, '1' after 700 ns;
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end tb; |