40 lines
804 B
VHDL
40 lines
804 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component LFSR is
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Port ( clk : in std_logic;
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value32 : out std_logic_vector (31 downto 0);
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value16 : out std_logic_vector (15 downto 0);
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value8 : out std_logic_vector ( 7 downto 0));
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk : std_logic;
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signal sig_r8 : std_logic_vector (7 downto 0);
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signal sig_r16 : std_logic_vector (15 downto 0);
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signal sig_r32 : std_logic_vector (31 downto 0);
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begin
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DUT: LFSR port map(
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clk => sig_clk,
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value32 => sig_r32,
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value16 => sig_r16,
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value8 => sig_r8
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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end tb; |