51 lines
882 B
VHDL
51 lines
882 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component single_port_rom is
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port
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(
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addr : in std_logic_vector(15 downto 0);
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clk : in std_logic;
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q : out std_logic_vector(7 downto 0)
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);
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk : std_logic;
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signal sig_addr : std_logic_vector(15 downto 0);
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signal sig_q : std_logic_vector(7 downto 0);
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begin
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DUT: single_port_rom port map(
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clk => sig_clk,
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addr => sig_addr,
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q => sig_q
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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stim: process
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begin
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sig_addr <= "0000000000000000";
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wait for 12 ns;
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sig_addr <= "0000000000000001";
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wait for 12 ns;
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sig_addr <= std_logic_vector(to_unsigned(10,16));
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wait;
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end process stim;
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end tb; |