commit e2ef356f1556669aa81f24094abe25d5397312bf Author: Maximilian Eibl Date: Mon Feb 10 20:28:13 2025 +0100 first commit diff --git a/01_Halfadder/.gitignore b/01_Halfadder/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/01_Halfadder/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/01_Halfadder/01_Halfadder.vhdpproj b/01_Halfadder/01_Halfadder.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/01_Halfadder/01_Halfadder.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/01_Halfadder/design.vhd b/01_Halfadder/design.vhd new file mode 100644 index 0000000..864e1dd --- /dev/null +++ b/01_Halfadder/design.vhd @@ -0,0 +1,19 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +-- Entity HA +entity halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end halfadder; + +-- Architecture HA +architecture behavior of halfadder is +begin + -- HA is made out of 2 gates: + sum_o <= a_i xor b_i; + cy_o <= a_i and b_i; +end behavior; \ No newline at end of file diff --git a/01_Halfadder/testbench.ghw b/01_Halfadder/testbench.ghw new file mode 100644 index 0000000..e453628 Binary files /dev/null and b/01_Halfadder/testbench.ghw differ diff --git a/01_Halfadder/testbench.vhd b/01_Halfadder/testbench.vhd new file mode 100644 index 0000000..0f2e843 --- /dev/null +++ b/01_Halfadder/testbench.vhd @@ -0,0 +1,38 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + +-- Entity TB +entity testbench is +-- empty +end testbench; + + +-- Architecture TB +architecture tb of testbench is + +-- DUT component declaration + component halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); + end component; + +-- declare signals + signal sig_a, sig_b, sig_sum, sig_cy: std_logic; + +begin + + -- DUT instantiation and port mapping + DUT: halfadder port map( + a_i => sig_a, + b_i => sig_b, + sum_o => sig_sum, + cy_o => sig_cy); + + -- apply testpattern + sig_a <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns; + sig_b <= '0', '1' after 200 ns; + +end tb; diff --git a/01_Halfadder/vhdl_ls.toml b/01_Halfadder/vhdl_ls.toml new file mode 100644 index 0000000..b6c38f9 --- /dev/null +++ b/01_Halfadder/vhdl_ls.toml @@ -0,0 +1,12 @@ +# auto-generated +[Libraries] +work.files = [ + 'design.vhd', + 'testbench.vhd' +] +[libraries.work] +files = [ + 'design.vhd', + 'testbench.vhd' +] +# auto-generated-end \ No newline at end of file diff --git a/02_Fulladder/.gitignore b/02_Fulladder/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/02_Fulladder/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/02_Fulladder/02_Fulladder.vhdpproj b/02_Fulladder/02_Fulladder.vhdpproj new file mode 100644 index 0000000..d7384b9 --- /dev/null +++ b/02_Fulladder/02_Fulladder.vhdpproj @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/02_Fulladder/design.vhd b/02_Fulladder/design.vhd new file mode 100644 index 0000000..aa63f6e --- /dev/null +++ b/02_Fulladder/design.vhd @@ -0,0 +1 @@ +-- empty: NOT EVEN library (otherwise compiler error) \ No newline at end of file diff --git a/02_Fulladder/fulladder.vhd b/02_Fulladder/fulladder.vhd new file mode 100644 index 0000000..daf599b --- /dev/null +++ b/02_Fulladder/fulladder.vhd @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity fulladder is + port (afa_i : in std_logic; + bfa_i : in std_logic; + cinfa_i : in std_logic; + sumfa_o : out std_logic; + coutfa_o : out std_logic); +end fulladder; + +architecture fa_behaviour of fulladder is + +-- Halfadder component + component halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); + end component; + + signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic; + +begin + +-- Instances of two halfadders + HA1: halfadder port map( + a_i => afa_i, + b_i => bfa_i, + sum_o => sig_ha1e, + cy_o => sig_ha1c); + + HA2: halfadder port map( + a_i => sig_ha1e, + b_i => cinfa_i, + sum_o => sumfa_o, + cy_o => sig_ha2c); + +-- The OR gate + coutfa_o <= sig_ha1c OR sig_ha2c; + +end fa_behaviour; \ No newline at end of file diff --git a/02_Fulladder/halfadder.vhd b/02_Fulladder/halfadder.vhd new file mode 100644 index 0000000..3424cb8 --- /dev/null +++ b/02_Fulladder/halfadder.vhd @@ -0,0 +1,16 @@ +-- The halfadder design +library IEEE; +use IEEE.std_logic_1164.all; + +entity halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end halfadder; + +architecture behavior of halfadder is +begin + sum_o <= a_i xor b_i; + cy_o <= a_i and b_i; +end behavior; \ No newline at end of file diff --git a/02_Fulladder/testbench.vhd b/02_Fulladder/testbench.vhd new file mode 100644 index 0000000..484f3a5 --- /dev/null +++ b/02_Fulladder/testbench.vhd @@ -0,0 +1,34 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity testbench is +-- empty +end testbench; + +architecture tb of testbench is + -- DUT components + component fulladder is + port (afa_i : in std_logic; + bfa_i : in std_logic; + cinfa_i : in std_logic; + sumfa_o : out std_logic; + coutfa_o : out std_logic); + end component; + + signal sig_afa, sig_bfa, sig_cinfa, sig_sumfa, sig_coutfa: std_logic; + +begin + + -- Connect DUTs + DUT_s: fulladder port map( + afa_i => sig_afa, + bfa_i => sig_bfa, + cinfa_i => sig_cinfa, + sumfa_o => sig_sumfa, + coutfa_o => sig_coutfa); + + + sig_afa <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns,'0' after 400 ns, '1' after 500 ns, '0' after 600 ns, '1' after 700 ns; + sig_bfa <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 600 ns; + sig_cinfa <= '0', '1' after 400 ns; +end tb; diff --git a/02_Fulladder/vhdl_ls.toml b/02_Fulladder/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/02_Fulladder/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/03_MUX_Example/.gitignore b/03_MUX_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/03_MUX_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/03_MUX_Example/03_MUX_Example.vhdpproj b/03_MUX_Example/03_MUX_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/03_MUX_Example/03_MUX_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/03_MUX_Example/design.vhd b/03_MUX_Example/design.vhd new file mode 100644 index 0000000..4e4c34f --- /dev/null +++ b/03_MUX_Example/design.vhd @@ -0,0 +1,20 @@ + +library IEEE; +use IEEE.std_logic_1164.all; + + +entity myMux is + port (sel : in std_logic_vector(1 downto 0); + data1_i : in std_logic_vector(2 downto 0); + data2_i : in std_logic_vector(2 downto 0); + outp : out std_logic_vector(2 downto 0) ); +end myMux; + + +architecture behavior of myMux is + +begin + with sel select outp <= data1_i when "00", + data2_i when "01", + "010" when others; +end behavior; diff --git a/03_MUX_Example/testbench.vhd b/03_MUX_Example/testbench.vhd new file mode 100644 index 0000000..116b837 --- /dev/null +++ b/03_MUX_Example/testbench.vhd @@ -0,0 +1,39 @@ + +library IEEE; +use IEEE.std_logic_1164.all; + +entity testbench is +end testbench; + + +architecture tb of testbench is + +-- DUT component declaration +component myMux is +port (sel : in std_logic_vector(1 downto 0); + data1_i : in std_logic_vector(2 downto 0); + data2_i : in std_logic_vector(2 downto 0); + outp : out std_logic_vector(2 downto 0) ); +end component; + +signal sig1, sig2 : std_logic; +signal sig_sel : std_logic_vector(1 downto 0); +signal sig_data1, sig_data2, sig_outp : std_logic_vector(2 downto 0); + + +begin +-- DUT instance +DUT: myMux port map( + sel => sig_sel, + data1_i => sig_data1, + data2_i => sig_data2, + outp => sig_outp); + +sig_data1 <= "111"; +sig_data2 <= "000"; +sig_sel <= (sig2,sig1); + +sig1 <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns; +sig2 <= '0', '1' after 200 ns; + +end tb; \ No newline at end of file diff --git a/03_MUX_Example/vhdl_ls.toml b/03_MUX_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/03_MUX_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/04_ClockGen_Example/.gitignore b/04_ClockGen_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/04_ClockGen_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/04_ClockGen_Example/04_ClockGen_Example.vhdpproj b/04_ClockGen_Example/04_ClockGen_Example.vhdpproj new file mode 100644 index 0000000..0f8f11c --- /dev/null +++ b/04_ClockGen_Example/04_ClockGen_Example.vhdpproj @@ -0,0 +1,10 @@ + + + + + + + + testbench.vhd + + \ No newline at end of file diff --git a/04_ClockGen_Example/clkGen.vhd b/04_ClockGen_Example/clkGen.vhd new file mode 100644 index 0000000..e63528e --- /dev/null +++ b/04_ClockGen_Example/clkGen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; diff --git a/04_ClockGen_Example/design.vhd b/04_ClockGen_Example/design.vhd new file mode 100644 index 0000000..e69de29 diff --git a/04_ClockGen_Example/testbench.vhd b/04_ClockGen_Example/testbench.vhd new file mode 100644 index 0000000..4aba64c --- /dev/null +++ b/04_ClockGen_Example/testbench.vhd @@ -0,0 +1,23 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; + +begin + DUT: clkGen port map( + clk => sig_clk + ); + + +end tb; diff --git a/04_ClockGen_Example/vhdl_ls.toml b/04_ClockGen_Example/vhdl_ls.toml new file mode 100644 index 0000000..3d7c846 --- /dev/null +++ b/04_ClockGen_Example/vhdl_ls.toml @@ -0,0 +1,14 @@ +# auto-generated +[Libraries] +work.files = [ + 'clkGen.vhd', + 'design.vhd', + 'testbench.vhd' +] +[libraries.work] +files = [ + 'clkGen.vhd', + 'design.vhd', + 'testbench.vhd' +] +# auto-generated-end \ No newline at end of file diff --git a/05_Fulladder_allVariants/.gitignore b/05_Fulladder_allVariants/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/05_Fulladder_allVariants/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/05_Fulladder_allVariants/05_Fulladder_allVariants.vhdpproj b/05_Fulladder_allVariants/05_Fulladder_allVariants.vhdpproj new file mode 100644 index 0000000..ace605d --- /dev/null +++ b/05_Fulladder_allVariants/05_Fulladder_allVariants.vhdpproj @@ -0,0 +1,11 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/05_Fulladder_allVariants/design.vhd b/05_Fulladder_allVariants/design.vhd new file mode 100644 index 0000000..e69de29 diff --git a/05_Fulladder_allVariants/fulladder_process.vhd b/05_Fulladder_allVariants/fulladder_process.vhd new file mode 100644 index 0000000..c2708ba --- /dev/null +++ b/05_Fulladder_allVariants/fulladder_process.vhd @@ -0,0 +1,38 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity fulladder_proc is + port (afa_proc_i : in std_logic; + bfa_proc_i : in std_logic; + cinfa_proc_i : in std_logic; + sumfa_proc_o : out std_logic; + coutfa_proc_o : out std_logic); +end fulladder_proc; + +architecture beh of fulladder_proc is + +signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0); +signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0); + +begin + sig_INPUTS <= (cinfa_proc_i,bfa_proc_i,afa_proc_i); + + table : process (sig_INPUTS) + begin + IF (sig_INPUTS = "000") then sig_OUTPUTS <= "00"; + elsif (sig_INPUTS = "001") then sig_OUTPUTS <= "01"; + elsif (sig_INPUTS = "010") then sig_OUTPUTS <= "01"; + elsif (sig_INPUTS = "011") then sig_OUTPUTS <= "10"; + elsif (sig_INPUTS = "100") then sig_OUTPUTS <= "01"; + elsif (sig_INPUTS = "101") then sig_OUTPUTS <= "10"; + elsif (sig_INPUTS = "110") then sig_OUTPUTS <= "10"; + elsif (sig_INPUTS = "111") then sig_OUTPUTS <= "11"; + else sig_OUTPUTS <= "XX"; end if; + + end process table; + + + sumfa_proc_o <= sig_OUTPUTS(0); + coutfa_proc_o <= sig_OUTPUTS(1); +end beh; \ No newline at end of file diff --git a/05_Fulladder_allVariants/fulladder_select.vhd b/05_Fulladder_allVariants/fulladder_select.vhd new file mode 100644 index 0000000..2edad24 --- /dev/null +++ b/05_Fulladder_allVariants/fulladder_select.vhd @@ -0,0 +1,34 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity fulladder_sel is + port (afa_sel_i : in std_logic; + bfa_sel_i : in std_logic; + cinfa_sel_i : in std_logic; + sumfa_sel_o : out std_logic; + coutfa_sel_o : out std_logic); +end fulladder_sel; + +architecture behavior of fulladder_sel is + +signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0); +signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0); + +begin + sig_INPUTS <= (cinfa_sel_i,bfa_sel_i,afa_sel_i); + + with sig_INPUTS select + sig_OUTPUTS <= "00" when "000", + "01" when "001", + "01" when "010", + "10" when "011", + "01" when "100", + "10" when "101", + "10" when "110", + "11" when "111", + "XX" when others; + + sumfa_sel_o <= sig_OUTPUTS(0); + coutfa_sel_o <= sig_OUTPUTS(1); +end behavior; \ No newline at end of file diff --git a/05_Fulladder_allVariants/fulladder_struct.vhd b/05_Fulladder_allVariants/fulladder_struct.vhd new file mode 100644 index 0000000..388fc63 --- /dev/null +++ b/05_Fulladder_allVariants/fulladder_struct.vhd @@ -0,0 +1,43 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity fulladder_struct is + port (afa_s_i : in std_logic; + bfa_s_i : in std_logic; + cinfa_s_i : in std_logic; + sumfa_s_o : out std_logic; + coutfa_s_o : out std_logic); +end fulladder_struct; + +architecture structural of fulladder_struct is + +-- Halfadder component +component halfadder is +port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end component; + +signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic; + +begin + +-- Instances of two halfadders + HA1: halfadder port map( + a_i => afa_s_i, + b_i => bfa_s_i, + sum_o => sig_ha1e, + cy_o => sig_ha1c); + + HA2: halfadder port map( + a_i => sig_ha1e, + b_i => cinfa_s_i, + sum_o => sumfa_s_o, + cy_o => sig_ha2c); + +-- The OR gate + coutfa_s_o <= sig_ha1c OR sig_ha2c; + +end structural; \ No newline at end of file diff --git a/05_Fulladder_allVariants/halfadder.vhd b/05_Fulladder_allVariants/halfadder.vhd new file mode 100644 index 0000000..2cba44c --- /dev/null +++ b/05_Fulladder_allVariants/halfadder.vhd @@ -0,0 +1,16 @@ +-- The halfadder design +library IEEE; +use IEEE.std_logic_1164.all; + +entity halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end halfadder; + +architecture behavior of halfadder is +begin + sum_o <= a_i xor b_i; + cy_o <= a_i and b_i; +end behavior; \ No newline at end of file diff --git a/05_Fulladder_allVariants/testbench.vhd b/05_Fulladder_allVariants/testbench.vhd new file mode 100644 index 0000000..56af80e --- /dev/null +++ b/05_Fulladder_allVariants/testbench.vhd @@ -0,0 +1,141 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + +entity testbench is +-- empty +end testbench; + +architecture tb of testbench is +-- DUT components +component fulladder_struct is + port (afa_s_i : in std_logic; + bfa_s_i : in std_logic; + cinfa_s_i : in std_logic; + sumfa_s_o : out std_logic; + coutfa_s_o : out std_logic); +end component; + +component fulladder_sel is + port (afa_sel_i : in std_logic; + bfa_sel_i : in std_logic; + cinfa_sel_i : in std_logic; + sumfa_sel_o : out std_logic; + coutfa_sel_o : out std_logic); +end component; + +component fulladder_proc is + port (afa_proc_i : in std_logic; + bfa_proc_i : in std_logic; + cinfa_proc_i : in std_logic; + sumfa_proc_o : out std_logic; + coutfa_proc_o : out std_logic); +end component; + + + +signal sig_afa_s, sig_bfa_s, sig_cinfa_s, sig_sumfa_s, sig_coutfa_s: std_logic; +signal sig_afa_sel, sig_bfa_sel, sig_cinfa_sel, sig_sumfa_sel, sig_coutfa_sel: std_logic; +signal sig_afa_proc, sig_bfa_proc, sig_cinfa_proc, sig_sumfa_proc, sig_coutfa_proc: std_logic; + +begin + + -- Connect DUTs + DUT_s: fulladder_struct port map( + afa_s_i => sig_afa_s, + bfa_s_i => sig_bfa_s, + cinfa_s_i => sig_cinfa_s, + sumfa_s_o => sig_sumfa_s, + coutfa_s_o => sig_coutfa_s); + + DUT_sel: fulladder_sel port map( + afa_sel_i => sig_afa_sel, + bfa_sel_i => sig_bfa_sel, + cinfa_sel_i => sig_cinfa_sel, + sumfa_sel_o => sig_sumfa_sel, + coutfa_sel_o => sig_coutfa_sel); + + DUT_proc: fulladder_proc port map( + afa_proc_i => sig_afa_proc, + bfa_proc_i => sig_bfa_proc, + cinfa_proc_i => sig_cinfa_proc, + sumfa_proc_o => sig_sumfa_proc, + coutfa_proc_o => sig_coutfa_proc); + + stim :process is + + begin + + sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '0'; + sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0'; + sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 000 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 000 NOK" severity failure; + + sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '0'; + sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0'; + sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 001 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 001 NOK" severity failure; + + sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '0'; + sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0'; + sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 010 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 010 NOK" severity failure; + + sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '0'; + sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0'; + sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 011 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 011 NOK" severity failure; + + sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '1'; + sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1'; + sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 100 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 100 NOK" severity failure; + + sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '1'; + sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1'; + sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 101 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 101 NOK" severity failure; + + sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '1'; + sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1'; + sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 110 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 110 NOK" severity failure; + + sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '1'; + sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1'; + sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1'; + + wait for 10 ns; + assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 111 NOK" severity failure; + assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 111 NOK" severity failure; + + wait; + + end process stim; + + + + + +end tb; diff --git a/05_Fulladder_allVariants/vhdl_ls.toml b/05_Fulladder_allVariants/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/05_Fulladder_allVariants/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/06_VELS_Example/.gitignore b/06_VELS_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/06_VELS_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/06_VELS_Example/06_VELS_Example.vhdpproj b/06_VELS_Example/06_VELS_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/06_VELS_Example/06_VELS_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/06_VELS_Example/design.vhd b/06_VELS_Example/design.vhd new file mode 100644 index 0000000..c2a09f0 --- /dev/null +++ b/06_VELS_Example/design.vhd @@ -0,0 +1,13 @@ +-- be aware of the correct order! +-- EDA compiles from left to right + +-- 1) gate entities +-- 2) architectures for the gate entities +-- 3) Package (must be done after 1, because otherwise componante is not known) +-- 4) your entity +-- 5) your architecture (needs to know all above) +-- 6) Testbench Entity +-- 7) Testbench Architecture (in same file as testbench entity) + + +-- This example is related to the first VELS taks using packages (if there is no package, skip step 1-3) \ No newline at end of file diff --git a/06_VELS_Example/testbench.vhd b/06_VELS_Example/testbench.vhd new file mode 100644 index 0000000..57c6acc --- /dev/null +++ b/06_VELS_Example/testbench.vhd @@ -0,0 +1,74 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.std_artih.all; + + +entity testbench is +end testbench; + + +architecture tb of testbench is + + -- declare your DUT + component gates is + port( A,B,C,D : in std_logic; + O : out std_logic); + end component; + + + -- needed signals + signal sig_A, sig_B, sig_C, sig_D, sig_O: std_logic; + + begin + + -- Connect DUT with tb signals + DUT: gates port map( + A => sig_A, + B => sig_B, + C => sig_C, + D => sig_D, + O => sig_O); + + -- define process for testing our DUT + gate_tester : process + + -- define a procedure (Slides 07) that applys input vector, waits and than checks output + procedure check_sample(val_A, val_B, val_C, val_D, val_O : in std_logic) is + begin + + -- apply signals to DUT inputs + sig_A <= val_A; + sig_B <= val_B; + sig_C <= val_C; + sig_D <= val_D; + + -- wait (at least 1 delta cycle) + wait for 10 ns; + + -- check output of DUT and report possible error message + assert (sig_O = val_O) report "Error for A= " + & std_logic'image(val_A) & " B= " + & std_logic'image(val_B) & " C= " + & std_logic'image(val_C) & " D= " + & std_logic'image(val_D) & ". Output is " + & std_logic'image(sig_O) & " but should be " + & std_logic'image(val_O) & "." + severity failure; + + end procedure check_sample; + + begin + + -- now use procedure to check different combinations + -- change this according to your solution + -- (can also be done with loop, but we havn't learned that yet) + check_sample('0','0','0','0','1'); + check_sample('0','0','0','1','0'); + check_sample('1','1','1','1','1'); + + -- wait forever to stop process + wait; + + end process gate_tester; + +end tb; diff --git a/06_VELS_Example/vhdl_ls.toml b/06_VELS_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/06_VELS_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/07_DTime_GateDelay_Example/.gitignore b/07_DTime_GateDelay_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/07_DTime_GateDelay_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/07_DTime_GateDelay_Example/07_DTime_GateDelay_Example.vhdpproj b/07_DTime_GateDelay_Example/07_DTime_GateDelay_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/07_DTime_GateDelay_Example/07_DTime_GateDelay_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/07_DTime_GateDelay_Example/design.vhd b/07_DTime_GateDelay_Example/design.vhd new file mode 100644 index 0000000..6feeb3e --- /dev/null +++ b/07_DTime_GateDelay_Example/design.vhd @@ -0,0 +1,17 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity log is + port (inp : in std_logic; + C : out std_logic); +end log; + +architecture behavior of log is +signal A,B : std_logic; +begin + A <= NOT inp after 1 ns; + B <= A NAND '1' after 1 ns; + C <= A AND B after 1 ns; +end behavior; diff --git a/07_DTime_GateDelay_Example/testbench.vhd b/07_DTime_GateDelay_Example/testbench.vhd new file mode 100644 index 0000000..2b4a8d3 --- /dev/null +++ b/07_DTime_GateDelay_Example/testbench.vhd @@ -0,0 +1,25 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +-- empty +end testbench; + +architecture tb of testbench is + +component log is +port (inp : in std_logic; + C : out std_logic); +end component; +signal inp_in, C_in : std_logic; + +begin + DUT: log port map( + inp => inp_in, + C => C_in + ); + inp_in <= '1', '0' after 10 ns, '1' after 20 ns; + +end tb; \ No newline at end of file diff --git a/07_DTime_GateDelay_Example/vhdl_ls.toml b/07_DTime_GateDelay_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/07_DTime_GateDelay_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/08_InfereredLatch_Example/.gitignore b/08_InfereredLatch_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/08_InfereredLatch_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/08_InfereredLatch_Example/08_InfereredLatch_Example.vhdpproj b/08_InfereredLatch_Example/08_InfereredLatch_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/08_InfereredLatch_Example/08_InfereredLatch_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/08_InfereredLatch_Example/design.vhd b/08_InfereredLatch_Example/design.vhd new file mode 100644 index 0000000..1d30580 --- /dev/null +++ b/08_InfereredLatch_Example/design.vhd @@ -0,0 +1,21 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity InfLatch is +port ( D:in std_logic; + En:in std_logic; + Q:out std_logic); +end InfLatch; + +architecture beh of InfLatch is +begin + +p0: process (D,En) +begin + if En= '1' then + Q <= D; + end if; +end process p0; + +end beh; \ No newline at end of file diff --git a/08_InfereredLatch_Example/testbench.vhd b/08_InfereredLatch_Example/testbench.vhd new file mode 100644 index 0000000..5fdf06a --- /dev/null +++ b/08_InfereredLatch_Example/testbench.vhd @@ -0,0 +1,46 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +-- empty +end testbench; + +architecture tb of testbench is + +component InfLatch is +port ( D:in std_logic; + En:in std_logic; + Q:out std_logic); +end component; + +signal sig_D, sig_En, sig_Q : std_logic; + +begin + DUT: InfLatch port map( + D => sig_D, + En => sig_en, + Q => sig_Q + ); + +stim : process +begin + sig_D <= '1'; + sig_EN <= '0'; + wait for 10 ns; + sig_En <= '1'; + wait for 2 ns; + sig_D <= '0'; + wait for 2 ns; + sig_D <= '1'; + wait for 10 ns; + sig_En <= '0'; + wait for 2 ns; + sig_D <= '0'; + wait for 2 ns; + sig_D <= '1'; + wait; +end process stim; + +end tb; \ No newline at end of file diff --git a/08_InfereredLatch_Example/vhdl_ls.toml b/08_InfereredLatch_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/08_InfereredLatch_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/09_DFF_Example/.gitignore b/09_DFF_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/09_DFF_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/09_DFF_Example/09_DFF_Example.vhdpproj b/09_DFF_Example/09_DFF_Example.vhdpproj new file mode 100644 index 0000000..ece8b06 --- /dev/null +++ b/09_DFF_Example/09_DFF_Example.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/09_DFF_Example/clkgen.vhd b/09_DFF_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/09_DFF_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/09_DFF_Example/design.vhd b/09_DFF_Example/design.vhd new file mode 100644 index 0000000..6eb1437 --- /dev/null +++ b/09_DFF_Example/design.vhd @@ -0,0 +1,24 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity myDFF is +port ( clk:in std_logic; + D:in std_logic; + reset:in std_logic; + Q:out std_logic); +end myDFF; + +architecture beh of myDFF is +begin + +DFF: process ( Clk, reset ) +begin + If reset ='1' then + Q <='0'; + Elsif (Clk'event and Clk ='1') then + Q <= D ; + end if ; +end process DFF; + +end beh; \ No newline at end of file diff --git a/09_DFF_Example/testbench.vhd b/09_DFF_Example/testbench.vhd new file mode 100644 index 0000000..f0db6b9 --- /dev/null +++ b/09_DFF_Example/testbench.vhd @@ -0,0 +1,60 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component myDFF is +port ( clk:in std_logic; + D:in std_logic; + reset:in std_logic; + Q:out std_logic); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_D, sig_clk, sig_Q, sig_reset : std_logic; + +begin + DUT: myDFF port map( + clk => sig_clk, + D => sig_D, + reset => sig_reset, + Q => sig_Q + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +res_stim : process +begin + sig_reset <= '0'; + wait for 2 ns; + sig_reset <= '1'; + wait for 10 ns; + sig_reset <= '0'; + wait for 20 ns; + sig_reset <= '1'; + wait for 1 ns; + sig_reset <= '0'; + wait; +end process res_stim; + +d_stim : process +begin + sig_D <= '0'; + wait for 17 ns; + sig_D <= '1'; + wait for 30 ns; + sig_D <= '0'; + wait; +end process d_stim; + +end tb; \ No newline at end of file diff --git a/09_DFF_Example/vhdl_ls.toml b/09_DFF_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/09_DFF_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/10_LFSR_Example/.gitignore b/10_LFSR_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/10_LFSR_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/10_LFSR_Example/10_LFSR_Example.vhdpproj b/10_LFSR_Example/10_LFSR_Example.vhdpproj new file mode 100644 index 0000000..ece8b06 --- /dev/null +++ b/10_LFSR_Example/10_LFSR_Example.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/10_LFSR_Example/clkgen.vhd b/10_LFSR_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/10_LFSR_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/10_LFSR_Example/design.vhd b/10_LFSR_Example/design.vhd new file mode 100644 index 0000000..8b0a8aa --- /dev/null +++ b/10_LFSR_Example/design.vhd @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity LFSR is + Port ( clk : in std_logic; + value32 : out std_logic_vector (31 downto 0); + value16 : out std_logic_vector (15 downto 0); + value8 : out std_logic_vector ( 7 downto 0)); +end LFSR; + +architecture Behavioral of LFSR is +signal rnd32 : std_logic_vector (31 downto 0) := (others=>'0'); +signal rnd16 : std_logic_vector (15 downto 0) := (others=>'0'); +signal rnd8 : std_logic_vector ( 7 downto 0) := (others=>'0'); +begin + process begin + wait until rising_edge(CLK); + -- 8Bit + rnd8(7 downto 1) <= rnd8(6 downto 0) ; + rnd8(0) <= not(rnd8(7) XOR rnd8(6) XOR rnd8(4)); + -- 16Bit + rnd16(15 downto 1) <= rnd16(14 downto 0) ; + rnd16(0) <= not(rnd16(15) XOR rnd16(14) XOR rnd16(13) XOR rnd16(4)); + -- 32 Bit + rnd32(31 downto 1) <= rnd32(30 downto 0) ; + rnd32(0) <= not(rnd32(31) XOR rnd32(22) XOR rnd32(2) XOR rnd32(1)); + end process; + value32 <= rnd32; + value16 <= rnd16; + value8 <= rnd8; +end Behavioral; \ No newline at end of file diff --git a/10_LFSR_Example/testbench.vhd b/10_LFSR_Example/testbench.vhd new file mode 100644 index 0000000..63384ca --- /dev/null +++ b/10_LFSR_Example/testbench.vhd @@ -0,0 +1,40 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component LFSR is +Port ( clk : in std_logic; + value32 : out std_logic_vector (31 downto 0); + value16 : out std_logic_vector (15 downto 0); + value8 : out std_logic_vector ( 7 downto 0)); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; +signal sig_r8 : std_logic_vector (7 downto 0); +signal sig_r16 : std_logic_vector (15 downto 0); +signal sig_r32 : std_logic_vector (31 downto 0); + +begin + DUT: LFSR port map( + clk => sig_clk, + value32 => sig_r32, + value16 => sig_r16, + value8 => sig_r8 + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + + +end tb; \ No newline at end of file diff --git a/10_LFSR_Example/vhdl_ls.toml b/10_LFSR_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/10_LFSR_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/11_MinArith/.gitignore b/11_MinArith/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/11_MinArith/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/11_MinArith/11_MinArith.vhdpproj b/11_MinArith/11_MinArith.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/11_MinArith/11_MinArith.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/11_MinArith/design.vhd b/11_MinArith/design.vhd new file mode 100644 index 0000000..a8704e2 --- /dev/null +++ b/11_MinArith/design.vhd @@ -0,0 +1,25 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity minArith is + port (a_i : in std_logic_vector (7 downto 0); + b_i : in std_logic_vector (7 downto 0); + ssum_o : out std_logic_vector (7 downto 0); + sdiff_o : out std_logic_vector (7 downto 0); + usum_o : out std_logic_vector (7 downto 0); + udiff_o : out std_logic_vector (7 downto 0); + ainc_o : out std_logic_vector (7 downto 0)); +end minArith; + +-- behavioral description of the halfadder given by two gates +architecture behavior of minArith is +begin + ssum_o <= std_logic_vector(signed(a_i) + signed(b_i)); + sdiff_o <= std_logic_vector(signed(a_i) - signed(b_i)); + usum_o <= std_logic_vector(unsigned(a_i) + unsigned(b_i)); + udiff_o <= std_logic_vector(unsigned(a_i) - unsigned(b_i)); + ainc_o <= std_logic_vector(unsigned(a_i) + "00000001"); + +end behavior; \ No newline at end of file diff --git a/11_MinArith/testbench.vhd b/11_MinArith/testbench.vhd new file mode 100644 index 0000000..5ab1309 --- /dev/null +++ b/11_MinArith/testbench.vhd @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + + +architecture tb of testbench is + +component minArith is +port (a_i : in std_logic_vector (7 downto 0); + b_i : in std_logic_vector (7 downto 0); + ssum_o : out std_logic_vector (7 downto 0); + sdiff_o : out std_logic_vector (7 downto 0); + usum_o : out std_logic_vector (7 downto 0); + udiff_o : out std_logic_vector (7 downto 0); + ainc_o : out std_logic_vector (7 downto 0)); +end component; + + +signal sig_a, sig_b, sig_ssum, sig_sdiff, sig_usum, sig_udiff, sig_ainc : std_logic_vector(7 downto 0); + +begin + + DUT: minArith port map( + a_i => sig_a, + b_i => sig_b, + ssum_o => sig_ssum, + sdiff_o => sig_sdiff, + usum_o => sig_usum, + udiff_o => sig_udiff, + ainc_o => sig_ainc ); + + + + sig_a <= "00000001", "00000010" after 100 ns, "00001010" after 200 ns; + sig_b <= "00000001", "00000011" after 100 ns, "00100010" after 200 ns; + +end tb; diff --git a/11_MinArith/vhdl_ls.toml b/11_MinArith/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/11_MinArith/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/12_HA_with_assert_tb_Example/.gitignore b/12_HA_with_assert_tb_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/12_HA_with_assert_tb_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/12_HA_with_assert_tb_Example/12_HA_with_assert_tb_Example.vhdpproj b/12_HA_with_assert_tb_Example/12_HA_with_assert_tb_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/12_HA_with_assert_tb_Example/12_HA_with_assert_tb_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/12_HA_with_assert_tb_Example/design.vhd b/12_HA_with_assert_tb_Example/design.vhd new file mode 100644 index 0000000..10968ca --- /dev/null +++ b/12_HA_with_assert_tb_Example/design.vhd @@ -0,0 +1,18 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +-- entity of the halfadder +-- 2 inputs, 2 outputs, both of type IEEE1164 std_logic +entity halfadder is + port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end halfadder; + +-- behavioral description of the halfadder given by two gates +architecture behavior of halfadder is +begin + sum_o <= a_i xor b_i; + cy_o <= a_i and b_i; +end behavior; \ No newline at end of file diff --git a/12_HA_with_assert_tb_Example/testbench.vhd b/12_HA_with_assert_tb_Example/testbench.vhd new file mode 100644 index 0000000..475a293 --- /dev/null +++ b/12_HA_with_assert_tb_Example/testbench.vhd @@ -0,0 +1,70 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +-- the entity of the testbench is empty, no connection to the outer world +entity testbench is +end testbench; + + +architecture tb of testbench is +-- DUT (device under test = halfadder) component declaration +component halfadder is +port (a_i : in std_logic; + b_i : in std_logic; + sum_o : out std_logic; + cy_o : out std_logic); +end component; + +-- signals for the testbench +signal sig_a, sig_b, sig_sum_out, sig_cy_out: std_logic; + +begin + + -- Connect DUT with tb signals + DUT: halfadder port map( + a_i => sig_a, + b_i => sig_b, + sum_o => sig_sum_out, + cy_o => sig_cy_out); + + -- Process for DUT Test + stimTest : process + + -- Procedure for applying an input vector + procedure applyTv(inputs : in std_logic_vector (1 downto 0)) is + begin + sig_a <= inputs(0); + sig_b <= inputs(1); + wait for 10 ns; + end procedure applyTv; + + -- Procedure for checking the outputs + procedure check(outputs : in std_logic_vector (1 downto 0)) is + begin + + assert (sig_sum_out = outputs(0)) + report "Testpattern " & std_logic'image(sig_a) & " " & std_logic'image(sig_b) & " Error in sum_out got " & std_logic'image(sig_sum_out) & " expected " & std_logic'image(outputs(0)) severity error; + + assert (sig_cy_out = outputs(1)) + report "Testpattern " & std_logic'image(sig_b) & " " & std_logic'image(sig_a) & " Error in cy_out got " & std_logic'image(sig_cy_out) & " expected " & std_logic'image(outputs(1)) severity error; + + end procedure check; + + + + begin + + -- Let's apply different input vectors and check the output + applyTv("00"); + check("00"); + applyTv("01"); + check("01"); + applyTv("10"); + check("01"); + applyTv("11"); + check("10"); + wait; + + end process stimTest; + +end tb; diff --git a/12_HA_with_assert_tb_Example/vhdl_ls.toml b/12_HA_with_assert_tb_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/12_HA_with_assert_tb_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/13_procedure_Example/.gitignore b/13_procedure_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/13_procedure_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/13_procedure_Example/13_procedure_Example.vhdpproj b/13_procedure_Example/13_procedure_Example.vhdpproj new file mode 100644 index 0000000..38d1ce5 --- /dev/null +++ b/13_procedure_Example/13_procedure_Example.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/13_procedure_Example/design.vhd b/13_procedure_Example/design.vhd new file mode 100644 index 0000000..d3ed9c1 --- /dev/null +++ b/13_procedure_Example/design.vhd @@ -0,0 +1,14 @@ +library IEEE; +use IEEE.std_logic_1164.all; + + +entity MyDesign is + port (clk_i : in std_logic; + data_i : in std_logic); +end MyDesign; + + +architecture behavior of MyDesign is +begin + +end behavior; \ No newline at end of file diff --git a/13_procedure_Example/testbench.vhd b/13_procedure_Example/testbench.vhd new file mode 100644 index 0000000..26992e0 --- /dev/null +++ b/13_procedure_Example/testbench.vhd @@ -0,0 +1,108 @@ +library IEEE; +use IEEE.std_logic_1164.all; +--use IEEE.std_artih.all; + + +entity testbench is +end testbench; + + +architecture tb of testbench is + +component MyDesign is +port (clk_i : in std_logic; + data_i : in std_logic); +end component; + + + +signal sig_data, sig_clk: std_logic; +signal send_count : integer :=0; + +begin + + -- Connect DUT with tb signals + DUT: MyDesign port map( + clk_i => sig_clk, + data_i => sig_data); + + stimTest : process + + procedure send(d0,d1,d2,d3 : in std_logic) is + begin + + if (send_count=0) then + assert ((d0='1') AND (d1='1') AND (d2='1') AND (d3='1')) report "error in first frame (d0,d1,d2,d3) is " + & std_logic'image(d0) + & std_logic'image(d1) + & std_logic'image(d2) + & std_logic'image(d3) + severity error; + end if; + + wait for 4 ms; + + sig_data <= '0'; + sig_clk <= '1'; + + for I in 0 to 3 loop + wait for 1 ms; + sig_clk <= NOT sig_clk; + end loop; + + sig_data <= d0; + sig_clk <= '1'; + wait for 1 ms; + sig_clk <= '0'; + wait for 1 ms; + + sig_data <= d1; + sig_clk <= '1'; + wait for 1 ms; + sig_clk <= '0'; + wait for 1 ms; + + sig_data <= d2; + sig_clk <= '1'; + wait for 1 ms; + sig_clk <= '0'; + wait for 1 ms; + + sig_data <= d3; + sig_clk <= '1'; + wait for 1 ms; + sig_clk <= '0'; + wait for 1 ms; + + sig_data <= '0'; + sig_clk <= '1'; + wait for 1 ms; + sig_clk <= '0'; + wait for 1 ms; + + sig_data <= '1'; + sig_clk <= '1'; + wait for 1ms; + sig_clk <= '0'; + + send_count <= send_count+1; + + end procedure send; + + + begin + + sig_clk <= '0'; + sig_data <= '1'; + + send('1','0','1','0'); + + wait for 10 ms; + + send('0','1','0','1'); + + + wait; + end process stimTest; + +end tb; diff --git a/13_procedure_Example/vhdl_ls.toml b/13_procedure_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/13_procedure_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/14_FSM_Moore_Example/.gitignore b/14_FSM_Moore_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/14_FSM_Moore_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/14_FSM_Moore_Example/14_FSM_Moore_Example.vhdpproj b/14_FSM_Moore_Example/14_FSM_Moore_Example.vhdpproj new file mode 100644 index 0000000..ece8b06 --- /dev/null +++ b/14_FSM_Moore_Example/14_FSM_Moore_Example.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/14_FSM_Moore_Example/clkgen.vhd b/14_FSM_Moore_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/14_FSM_Moore_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/14_FSM_Moore_Example/design.vhd b/14_FSM_Moore_Example/design.vhd new file mode 100644 index 0000000..b247d34 --- /dev/null +++ b/14_FSM_Moore_Example/design.vhd @@ -0,0 +1,81 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity FSM is + port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + start : in STD_LOGIC; + stop : in STD_LOGIC; + cout : out STD_LOGIC_VECTOR (2 downto 0)); +end FSM; + +architecture beh of FSM is + +type state_t is (cs_reset,cs_wait,cs_one,cs_two,cs_three,cs_four,cs_five); +signal state, next_state : state_t := cs_reset; + + +begin + +p_seq: process (clk,reset) +begin + if reset ='1' then + state <= cs_reset; + elsif (Clk'event and Clk ='1') then + state <= next_state; + end if; +end process p_seq; + +p_comb: process (state,start,stop) +begin + case state is + when cs_reset => next_state <= cs_wait; + cout <= "XXX"; + + when cs_wait => if (start='1' and stop='0') then + next_state <= cs_one; + else + next_state <= cs_wait; + end if; + cout <= "000"; + + when cs_one => if (stop='1') then + next_state <= cs_wait; + else + next_state <= cs_two; + end if; + cout <= "001"; + + + when cs_two => if (stop='1') then + next_state <= cs_wait; + else + next_state <= cs_three; + end if; + cout <= "010"; + + when cs_three => if (stop='1') then + next_state <= cs_wait; + else + next_state <= cs_four; + end if; + cout <= "011"; + + when cs_four => if (stop='1') then + next_state <= cs_wait; + else + next_state <= cs_five; + end if; + cout <= "100"; + + when cs_five => next_state <= cs_wait; + cout <= "101"; + + end case; + +end process p_comb; + + + +end beh; \ No newline at end of file diff --git a/14_FSM_Moore_Example/testbench.vhd b/14_FSM_Moore_Example/testbench.vhd new file mode 100644 index 0000000..97da47f --- /dev/null +++ b/14_FSM_Moore_Example/testbench.vhd @@ -0,0 +1,45 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component FSM is +port ( clk : in STD_LOGIC; + reset : in STD_LOGIC; + start : in STD_LOGIC; + stop : in STD_LOGIC; + cout : out STD_LOGIC_VECTOR (2 downto 0)); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk, sig_reset, sig_start, sig_stop : std_logic; +signal sig_cout : STD_LOGIC_VECTOR (2 downto 0); + +begin + DUT: FSM port map( + clk => sig_clk, + reset => sig_reset, + start => sig_start, + stop => sig_stop, + cout => sig_cout + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + + + +sig_start <= '0', '1' after 22 ns, '0' after 45 ns, '1' after 82 ns, '0' after 86 ns; + +sig_reset <='0','1' after 102 ns, '0' after 123 ns; +sig_stop <= '0', '1' after 58 ns, '0' after 68 ns; +end tb; \ No newline at end of file diff --git a/14_FSM_Moore_Example/vhdl_ls.toml b/14_FSM_Moore_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/14_FSM_Moore_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/15_FSM_Mealy_Example/.gitignore b/15_FSM_Mealy_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/15_FSM_Mealy_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj b/15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj new file mode 100644 index 0000000..17c77d7 --- /dev/null +++ b/15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj @@ -0,0 +1,9 @@ + + + + + + + + + \ No newline at end of file diff --git a/15_FSM_Mealy_Example/clkgen.vhd b/15_FSM_Mealy_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/15_FSM_Mealy_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/15_FSM_Mealy_Example/design.vhd b/15_FSM_Mealy_Example/design.vhd new file mode 100644 index 0000000..e69de29 diff --git a/15_FSM_Mealy_Example/fsm_syn.vhd b/15_FSM_Mealy_Example/fsm_syn.vhd new file mode 100644 index 0000000..545a307 --- /dev/null +++ b/15_FSM_Mealy_Example/fsm_syn.vhd @@ -0,0 +1,79 @@ +-- Code your design here +library IEEE; +use IEEE.std_logic_1164.all; + +entity FSM_sync is + port ( clk : in STD_LOGIC; + data_in : in STD_LOGIC; + direct : in STD_LOGIC; + invert : in STD_LOGIC; + data_out_sync : out STD_LOGIC); +end FSM_sync; + +architecture beh of FSM_sync is + + type state_t is (S_start,S_direct,S_invert); + + signal state : state_t := S_start; + signal next_state : state_t := S_start; + + signal dbg_state: std_logic_vector(1 downto 0); -- just for debugging (we can't see type state_t in the waveform viewer) + + signal next_data_out : std_logic := '0'; + +begin + + p_seq: process (clk) + begin + if (clk'event and clk ='1') then + state <= next_state; + data_out_sync <= next_data_out; + end if; + end process p_seq; + + + p_comb: process (state,data_in,direct,invert) + begin + case state is + when S_start => if direct AND NOT invert then + next_data_out <= data_in; + next_state <= S_direct; + elsif invert AND NOT direct then + next_data_out <= not data_in; + next_state <= S_invert; + else + next_data_out <= '0'; + next_state <= S_start; + end if; + + when S_direct => if direct and not invert then + next_state <= S_direct; + next_data_out <= data_in; + else + next_state <= S_start; + next_data_out <= '0'; + end if; + + when S_invert => if invert and not direct then + next_state <= S_invert; + next_data_out <= not data_in; + else + next_state <= S_start; + next_data_out <= '0'; + end if; + end case; + + end process p_comb; + + -- just for debugging, we transform the state (type state_t) to a 2bit vector, which we can see in the waveform viewer + dbg: process (state) + begin + case state is + when S_start => dbg_state <= "00"; + when S_direct => dbg_state <= "01"; + when S_invert => dbg_state <= "10"; + end case; + end process dbg; + + +end beh; \ No newline at end of file diff --git a/15_FSM_Mealy_Example/testbench.vhd b/15_FSM_Mealy_Example/testbench.vhd new file mode 100644 index 0000000..c9901c9 --- /dev/null +++ b/15_FSM_Mealy_Example/testbench.vhd @@ -0,0 +1,60 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component FSM is +port ( clk : in STD_LOGIC; + data_in : in STD_LOGIC; + direct : in STD_LOGIC; + invert : in STD_LOGIC; + data_out : out STD_LOGIC); +end component; + +component FSM_sync is +port ( clk : in STD_LOGIC; + data_in : in STD_LOGIC; + direct : in STD_LOGIC; + invert : in STD_LOGIC; + data_out_sync : out STD_LOGIC); +end component; + + + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk, sig_din,sig_dout, sig_dout_sync, sig_direct, sig_invert : std_logic; + + +begin + DUT: FSM port map( + clk => sig_clk, + direct => sig_direct, + invert => sig_invert, + data_in => sig_din, + data_out => sig_dout + ); + + DUT_sync: FSM_sync port map( + clk => sig_clk, + direct => sig_direct, + invert => sig_invert, + data_in => sig_din, + data_out_sync => sig_dout_sync + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +sig_din <='0', '1' after 22 ns, '0' after 40 ns, '1' after 100 ns, '0' after 140 ns, '1' after 142 ns, '0' after 150 ns, '1' after 170 ns, '0' after 200 ns, '1' after 282 ns, '0' after 482 ns, '1' after 500 ns, '0' after 525 ns, '1' after 570 ns, '0' after 632ns, '1' after 750 ns; +sig_direct<= '0', '1' after 100 ns, '0' after 400 ns, '1' after 600 ns; +sig_invert<= '0', '1' after 350 ns, '0' after 650 ns, '1' after 700 ns; +end tb; \ No newline at end of file diff --git a/15_FSM_Mealy_Example/vhdl_ls.toml b/15_FSM_Mealy_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/15_FSM_Mealy_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/16_asyncROM_Example/.gitignore b/16_asyncROM_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/16_asyncROM_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/16_asyncROM_Example/16_asyncROM_Example.vhdpproj b/16_asyncROM_Example/16_asyncROM_Example.vhdpproj new file mode 100644 index 0000000..e12c55f --- /dev/null +++ b/16_asyncROM_Example/16_asyncROM_Example.vhdpproj @@ -0,0 +1,9 @@ + + + + + + + testbench.vhd + + \ No newline at end of file diff --git a/16_asyncROM_Example/design.vhd b/16_asyncROM_Example/design.vhd new file mode 100644 index 0000000..bdda6db --- /dev/null +++ b/16_asyncROM_Example/design.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity single_port_rom is + port + ( + addr : in std_logic_vector(3 downto 0); + q : out std_logic_vector(4 downto 0) + ); +end single_port_rom; + +architecture rtl of single_port_rom is + + -- Build a 2-D array type for the ROM + subtype word_t is std_logic_vector(4 downto 0); + type memory_t is array(0 to 15) of word_t; + + constant romdata : memory_t := ( + "10101", -- data for address 0 + "11111", -- data for address 1 + "10101", + "11110", + "10110", + "10101", + "11010", + "10010", + "10110", + "11101", + "10110", + "10111", + "00110", + "11101", + "10010", + "10110" -- data for address 15 + ); + +begin + q <= romdata(to_integer(unsigned(addr))); + +end rtl; \ No newline at end of file diff --git a/16_asyncROM_Example/testbench.ghw b/16_asyncROM_Example/testbench.ghw new file mode 100644 index 0000000..3b0f465 Binary files /dev/null and b/16_asyncROM_Example/testbench.ghw differ diff --git a/16_asyncROM_Example/testbench.vhd b/16_asyncROM_Example/testbench.vhd new file mode 100644 index 0000000..40e1de1 --- /dev/null +++ b/16_asyncROM_Example/testbench.vhd @@ -0,0 +1,47 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component single_port_rom is +port + ( + addr : in std_logic_vector(3 downto 0); + q : out std_logic_vector(4 downto 0) + ); +end component; + + +signal sig_addr : std_logic_vector(3 downto 0); +signal sig_q : std_logic_vector(4 downto 0); + + +begin + DUT: single_port_rom port map( + addr => sig_addr, + q => sig_q + ); + + + +stim: process +begin +sig_addr <= "0000"; +wait for 10 ns; +sig_addr <= "0001"; +wait for 10 ns; +sig_addr <= "0010"; +wait for 10 ns; +sig_addr <= "0100"; +wait for 10 ns; +sig_addr <= "1000"; +wait; +end process stim; + + +end tb; \ No newline at end of file diff --git a/16_asyncROM_Example/vhdl_ls.toml b/16_asyncROM_Example/vhdl_ls.toml new file mode 100644 index 0000000..b6c38f9 --- /dev/null +++ b/16_asyncROM_Example/vhdl_ls.toml @@ -0,0 +1,12 @@ +# auto-generated +[Libraries] +work.files = [ + 'design.vhd', + 'testbench.vhd' +] +[libraries.work] +files = [ + 'design.vhd', + 'testbench.vhd' +] +# auto-generated-end \ No newline at end of file diff --git a/17_syncROM_Example/.gitignore b/17_syncROM_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/17_syncROM_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/17_syncROM_Example/17_syncROM_Example.vhdpproj b/17_syncROM_Example/17_syncROM_Example.vhdpproj new file mode 100644 index 0000000..4ab5dc4 --- /dev/null +++ b/17_syncROM_Example/17_syncROM_Example.vhdpproj @@ -0,0 +1,10 @@ + + + + + + + + testbench.vhd + + \ No newline at end of file diff --git a/17_syncROM_Example/clkgen.vhd b/17_syncROM_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/17_syncROM_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/17_syncROM_Example/design.vhd b/17_syncROM_Example/design.vhd new file mode 100644 index 0000000..f07f22a --- /dev/null +++ b/17_syncROM_Example/design.vhd @@ -0,0 +1,45 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity single_port_rom is + port + ( + addr : in std_logic_vector(15 downto 0); + clk : in std_logic; + q : out std_logic_vector(7 downto 0) + ); +end single_port_rom; + +architecture rtl of single_port_rom is + + -- Build a 2-D array type for the RoM + subtype word_t is std_logic_vector(7 downto 0); + type memory_t is array(0 to 5) of word_t; + + constant romdata : memory_t := ( + X"FF", -- data for address 0 in HEX notation + X"A5", -- data for address 1 in HEX notation + X"AA", + X"B6", + X"5C", + X"23" + ); + + +begin + + process(clk) + variable addr_to_read : integer; + begin + if(rising_edge(clk)) then + addr_to_read := to_integer(unsigned(addr)); + if addr_to_read <= 5 then + q <= romdata(addr_to_read); + else + q <= "XXXXXXXX"; + end if; + end if; + end process; + +end rtl; \ No newline at end of file diff --git a/17_syncROM_Example/testbench.vhd b/17_syncROM_Example/testbench.vhd new file mode 100644 index 0000000..b8d9f7e --- /dev/null +++ b/17_syncROM_Example/testbench.vhd @@ -0,0 +1,51 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench is +end testbench; + +architecture tb of testbench is + +component single_port_rom is +port + ( + addr : in std_logic_vector(15 downto 0); + clk : in std_logic; + q : out std_logic_vector(7 downto 0) + ); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; +signal sig_addr : std_logic_vector(15 downto 0); +signal sig_q : std_logic_vector(7 downto 0); + + +begin + DUT: single_port_rom port map( + clk => sig_clk, + addr => sig_addr, + q => sig_q + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +stim: process +begin +sig_addr <= "0000000000000000"; +wait for 12 ns; +sig_addr <= "0000000000000001"; +wait for 12 ns; +sig_addr <= std_logic_vector(to_unsigned(10,16)); +wait; +end process stim; + + +end tb; \ No newline at end of file diff --git a/17_syncROM_Example/vhdl_ls.toml b/17_syncROM_Example/vhdl_ls.toml new file mode 100644 index 0000000..7c72fe6 --- /dev/null +++ b/17_syncROM_Example/vhdl_ls.toml @@ -0,0 +1,14 @@ +# auto-generated +[Libraries] +work.files = [ + 'clkgen.vhd', + 'design.vhd', + 'testbench.vhd' +] +[libraries.work] +files = [ + 'clkgen.vhd', + 'design.vhd', + 'testbench.vhd' +] +# auto-generated-end \ No newline at end of file diff --git a/18_RAM_Example/.gitignore b/18_RAM_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/18_RAM_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/18_RAM_Example/18_RAM_Example.vhdpproj b/18_RAM_Example/18_RAM_Example.vhdpproj new file mode 100644 index 0000000..ece8b06 --- /dev/null +++ b/18_RAM_Example/18_RAM_Example.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/18_RAM_Example/clkgen.vhd b/18_RAM_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/18_RAM_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/18_RAM_Example/design.vhd b/18_RAM_Example/design.vhd new file mode 100644 index 0000000..21ee0c8 --- /dev/null +++ b/18_RAM_Example/design.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity single_port_ram is + port + ( + data : in std_logic_vector(7 downto 0); + addr : in std_logic_vector(15 downto 0); + we : in std_logic; + clk : in std_logic; + q : out std_logic_vector(7 downto 0) + ); + +end entity; + +architecture rtl of single_port_ram is + + -- Build a 2-D array type for the RAM + subtype word_t is std_logic_vector(7 downto 0); + type memory_t is array(2**7-1 downto 0) of word_t; -- 2**7 = 128 + + signal ram : memory_t; + + -- Register to hold the address + signal addr_reg : std_logic_vector(15 downto 0); + +begin + + process(clk) + begin + if(rising_edge(clk)) then + if(we = '1') then + ram(to_integer(unsigned(addr))) <= data; + end if; + + -- Register the address for reading (synchron) + addr_reg <= addr; + end if; + + end process; + + -- asynchron data output (but attention: addr_reg changes synchronously) + q <= ram(to_integer(unsigned(addr_reg))); + +end rtl; diff --git a/18_RAM_Example/testbench.vhd b/18_RAM_Example/testbench.vhd new file mode 100644 index 0000000..b2ddd97 --- /dev/null +++ b/18_RAM_Example/testbench.vhd @@ -0,0 +1,95 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component single_port_ram is +port + ( + data : in std_logic_vector(7 downto 0); + addr : in std_logic_vector(15 downto 0); + we : in std_logic; + clk : in std_logic; + q : out std_logic_vector(7 downto 0) + ); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; +signal sig_addr : std_logic_vector(15 downto 0); +signal sig_q : std_logic_vector(7 downto 0); +signal sig_data : std_logic_vector(7 downto 0); +signal sig_we : std_logic; +use ieee.numeric_std.all; + +begin + DUT: single_port_ram port map( + clk => sig_clk, + addr => sig_addr, + data => sig_data, + we => sig_we, + q => sig_q + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +stim: process + + procedure ReadRAM(read_addr : in integer) is + begin + sig_we <= '0'; + sig_addr <= std_logic_vector(to_unsigned(read_addr,16)); + end procedure ReadRAM; + + procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is + begin + sig_we <= '1'; + sig_addr <= std_logic_vector(to_unsigned(write_addr,16)); + sig_data <= write_data; + end procedure WriteRAM; + + +begin + +wait for 7 ns; + +WriteRAM(2,"00000001"); +wait for 20 ns; +WriteRAM(4,"00000010"); +wait for 20 ns; +WriteRAM(6,"00000011"); +wait for 20 ns; +WriteRAM(8,"00000100"); +wait for 20 ns; +WriteRAM(10,"11111111"); +wait for 30 ns; + +ReadRAM(2); +wait for 20 ns; +ReadRAM(4); +wait for 20 ns; +ReadRAM(6); +wait for 20 ns; +ReadRAM(8); +wait for 20 ns; +ReadRAM(10); +wait for 20 ns; +ReadRAM(11); +wait for 20 ns; + + +wait; +end process stim; + + +end tb; \ No newline at end of file diff --git a/18_RAM_Example/vhdl_ls.toml b/18_RAM_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/18_RAM_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/19_RAMbus_Example/.gitignore b/19_RAMbus_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/19_RAMbus_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/19_RAMbus_Example/19_RAMbus_Example.vhdpproj b/19_RAMbus_Example/19_RAMbus_Example.vhdpproj new file mode 100644 index 0000000..ece8b06 --- /dev/null +++ b/19_RAMbus_Example/19_RAMbus_Example.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/19_RAMbus_Example/clkgen.vhd b/19_RAMbus_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/19_RAMbus_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/19_RAMbus_Example/design.vhd b/19_RAMbus_Example/design.vhd new file mode 100644 index 0000000..6ab41d6 --- /dev/null +++ b/19_RAMbus_Example/design.vhd @@ -0,0 +1,47 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity single_port_ram is + port + ( + data : inout std_logic_vector(7 downto 0); + addr : in std_logic_vector(15 downto 0); + cs : in std_logic; -- chip select + we : in std_logic; -- write enable + oe : in std_logic; -- output enable + clk : in std_logic + ); + +end entity; + +architecture rtl of single_port_ram is + + -- Build a 2-D array type for the RAM + subtype word_t is std_logic_vector(7 downto 0); + type memory_t is array(127 downto 0) of word_t; + + signal ram : memory_t; + +begin + + +wr: process (clk) begin + if (rising_edge(clk)) then + if ( cs = '1' and we = '1') then -- write (= ram stores data from data input) when we = 1 + ram(to_integer(unsigned(addr))) <= data; + end if; + end if; + end process; + +rd: process (clk) begin + if (rising_edge(clk)) then + if (cs = '1' and we = '0' and oe = '1') then -- read (= ram provides data at data ouput) only when we = 0 and oe = 1 + data <= ram(to_integer(unsigned(addr))); + else + data <= (others=>'Z'); -- IMPORTANT + end if; + end if; + end process; + +end rtl; diff --git a/19_RAMbus_Example/testbench.vhd b/19_RAMbus_Example/testbench.vhd new file mode 100644 index 0000000..9637c3c --- /dev/null +++ b/19_RAMbus_Example/testbench.vhd @@ -0,0 +1,104 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench is +end testbench; + +architecture tb of testbench is + +component single_port_ram is +port + ( + data : inout std_logic_vector(7 downto 0); + addr : in std_logic_vector(15 downto 0); + cs : in std_logic; + we : in std_logic; + oe : in std_logic; + clk : in std_logic + ); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; +signal sig_addr : std_logic_vector(15 downto 0); +signal sig_data : std_logic_vector(7 downto 0); +signal sig_we : std_logic; +signal sig_cs : std_logic; +signal sig_oe : std_logic; + + + +begin + DUT: single_port_ram port map( + clk => sig_clk, + addr => sig_addr, + data => sig_data, + we => sig_we, + cs => sig_cs, + oe => sig_oe + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +stim: process + + procedure ReadRAM(read_addr : in integer) is + begin + sig_data <= (others => 'Z'); + sig_we <= '0'; + sig_oe <= '1'; + sig_cs <= '1'; + sig_addr <= std_logic_vector(to_unsigned(read_addr,16)); + end procedure ReadRAM; + + procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is + begin + sig_we <= '1'; + sig_oe <= '0'; + sig_cs <= '1'; + sig_addr <= std_logic_vector(to_unsigned(write_addr,16)); + sig_data <= write_data; + end procedure WriteRAM; + + +begin + +wait for 7 ns; + +WriteRAM(2,"00000001"); +wait for 20 ns; +WriteRAM(4,"00000010"); +wait for 20 ns; +WriteRAM(6,"00000011"); +wait for 20 ns; +WriteRAM(8,"00000100"); +wait for 20 ns; +WriteRAM(10,"11111111"); +wait for 20 ns; + +ReadRAM(2); +wait for 20 ns; +ReadRAM(4); +wait for 20 ns; +ReadRAM(6); +wait for 20 ns; +ReadRAM(8); +wait for 20 ns; +ReadRAM(10); +wait for 20 ns; +ReadRAM(11); +wait for 20 ns; + + +wait; +end process stim; + + +end tb; \ No newline at end of file diff --git a/19_RAMbus_Example/vhdl_ls.toml b/19_RAMbus_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/19_RAMbus_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/20_pdRAM_Example/.gitignore b/20_pdRAM_Example/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/20_pdRAM_Example/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/20_pdRAM_Example/20_pdRAM_Example.vhdpproj b/20_pdRAM_Example/20_pdRAM_Example.vhdpproj new file mode 100644 index 0000000..4ab5dc4 --- /dev/null +++ b/20_pdRAM_Example/20_pdRAM_Example.vhdpproj @@ -0,0 +1,10 @@ + + + + + + + + testbench.vhd + + \ No newline at end of file diff --git a/20_pdRAM_Example/clkgen.vhd b/20_pdRAM_Example/clkgen.vhd new file mode 100644 index 0000000..0f197fc --- /dev/null +++ b/20_pdRAM_Example/clkgen.vhd @@ -0,0 +1,24 @@ +-- Clock Generator +library IEEE; +use IEEE.std_logic_1164.all; + + +entity clkGen is + port (clk : out std_logic); +end clkGen; + +architecture behavior of clkGen is + +constant clk_period : time := 10 ns; + +begin + clkgen : process + + begin + + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process clkgen; +end behavior; \ No newline at end of file diff --git a/20_pdRAM_Example/design.vhd b/20_pdRAM_Example/design.vhd new file mode 100644 index 0000000..8ea9216 --- /dev/null +++ b/20_pdRAM_Example/design.vhd @@ -0,0 +1,81 @@ + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; + +entity ram_dp is + port ( + clk :in std_logic; -- Clock Input + address_0 :in std_logic_vector (8-1 downto 0); -- address_0 Input + data_0 :inout std_logic_vector (8-1 downto 0); -- data_0 bi-directional + cs_0 :in std_logic; -- Chip Select + we_0 :in std_logic; -- Write Enable/Read Enable + oe_0 :in std_logic; -- Output Enable + address_1 :in std_logic_vector (8-1 downto 0); -- address_1 Input + data_1 :inout std_logic_vector (8-1 downto 0); -- data_1 bi-directional + cs_1 :in std_logic; -- Chip Select + we_1 :in std_logic; -- Write Enable/Read Enable + oe_1 :in std_logic -- Output Enable + ); +end entity; + + +architecture rtl of ram_dp is + ----------------Internal variables---------------- + constant RAM_DEPTH :integer := 2**8; + + signal data_0_out :std_logic_vector (8-1 downto 0); + signal data_1_out :std_logic_vector (8-1 downto 0); + + type RAM is array (integer range <>)of std_logic_vector (8-1 downto 0); + signal mem : RAM (0 to RAM_DEPTH-1); + +begin + ----------------Code Starts Here------------------ + + -- Memory Write Block (0 and 1) + MEM_WRITE: + process (clk) begin + if (rising_edge(clk)) then + if ( cs_0 = '1' and we_0 = '1') then + mem(conv_integer(address_0)) <= data_0; + elsif (cs_1 = '1' and we_1 = '1') then + mem(conv_integer(address_1)) <= data_1; + end if; + end if; + end process; + + + -- Memory Read Block 0 + MEM_READ_0: + process (clk) begin + if (rising_edge(clk)) then + if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then + data_0_out <= mem(conv_integer(address_0)); + else + data_0_out <= (others=>'0'); + end if; + end if; + end process; + + -- Memory Read Block 1 + MEM_READ_1: + process (clk) begin + if (rising_edge(clk)) then + if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then + data_1_out <= mem(conv_integer(address_1)); + else + data_1_out <= (others=>'0'); + end if; + end if; + end process; + + -- Tri-State Buffer control + -- output : When we_0 = 0, oe_0 = 1, cs_0 = 1 + data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z'); + --Second Port of RAM + -- output : When we_1 = 0, oe_1 = 1, cs_1 = 1 + data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z'); + + +end architecture; diff --git a/20_pdRAM_Example/testbench.vhd b/20_pdRAM_Example/testbench.vhd new file mode 100644 index 0000000..93eeb4b --- /dev/null +++ b/20_pdRAM_Example/testbench.vhd @@ -0,0 +1,87 @@ +-- Code your testbench here +library IEEE; +use IEEE.std_logic_1164.all; + + +entity testbench is +end testbench; + +architecture tb of testbench is + +component ram_dp is +port ( + clk :in std_logic; + address_0 :in std_logic_vector (8-1 downto 0); + data_0 :inout std_logic_vector (8-1 downto 0); + cs_0 :in std_logic; + we_0 :in std_logic; + oe_0 :in std_logic; + address_1 :in std_logic_vector (8-1 downto 0); + data_1 :inout std_logic_vector (8-1 downto 0); + cs_1 :in std_logic; + we_1 :in std_logic; + oe_1 :in std_logic + ); +end component; + +component clkGen is + port (clk : out std_logic); +end component; + +signal sig_clk : std_logic; + +signal sig_address_0 : std_logic_vector (8-1 downto 0); +signal sig_data_0 : std_logic_vector (8-1 downto 0); +signal sig_cs_0 : std_logic; +signal sig_we_0 : std_logic; +signal sig_oe_0 : std_logic; + +signal sig_address_1 : std_logic_vector (8-1 downto 0); +signal sig_data_1 : std_logic_vector (8-1 downto 0); +signal sig_cs_1 : std_logic; +signal sig_we_1 : std_logic; +signal sig_oe_1 : std_logic; + + +begin + DUT: ram_dp port map( + clk => sig_clk, + address_0 => sig_address_0, + data_0 => sig_data_0, + cs_0 => sig_cs_0, + we_0 => sig_we_0, + oe_0 => sig_oe_0, + address_1 => sig_address_1, + data_1 => sig_data_1, + cs_1 => sig_cs_1, + we_1 => sig_we_1, + oe_1 => sig_oe_1 + ); + + mClkGen : clkGen port map( + clk => sig_clk + ); + +stim: process +begin + + + sig_address_0 <= "00000000"; + sig_data_0 <= "00000000"; + sig_cs_0 <= '0'; + sig_we_0 <= '0'; + sig_oe_0 <= '0'; + sig_address_1 <="00000000"; + sig_data_1 <= "00000000"; + sig_cs_1 <= '0'; + sig_we_1 <= '0'; + sig_oe_1 <= '0'; + + + + +wait; +end process stim; + + +end tb; \ No newline at end of file diff --git a/20_pdRAM_Example/vhdl_ls.toml b/20_pdRAM_Example/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/20_pdRAM_Example/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task1/.gitignore b/Task1/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task1/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task1/IEEE_1164_Gates.vhdl b/Task1/IEEE_1164_Gates.vhdl new file mode 100644 index 0000000..1cc2263 --- /dev/null +++ b/Task1/IEEE_1164_Gates.vhdl @@ -0,0 +1,252 @@ +library ieee; +use ieee.std_logic_1164.all; + + +--########################## +--######## AND GATES ####### +--########################## + entity AND2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity AND2; + +library ieee; +use ieee.std_logic_1164.all; + + entity AND3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity AND3; + +library ieee; +use ieee.std_logic_1164.all; + + entity AND4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity AND4; + +--########################## +--######## NAND GATES ###### +--########################## + +library ieee; +use ieee.std_logic_1164.all; + + entity NAND2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity NAND2; + +library ieee; +use ieee.std_logic_1164.all; + + entity NAND3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity NAND3; + +library ieee; +use ieee.std_logic_1164.all; + + entity NAND4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity NAND4; + +--########################## +--######## OR GATES ######## +--########################## +library ieee; +use ieee.std_logic_1164.all; + + entity OR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity OR2; + +library ieee; +use ieee.std_logic_1164.all; + + entity OR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity OR3; + +library ieee; +use ieee.std_logic_1164.all; + + entity OR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity OR4; + +--########################## +--######## NOR GATES ####### +--########################## +library ieee; +use ieee.std_logic_1164.all; + entity NOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity NOR2; + +library ieee; +use ieee.std_logic_1164.all; + + entity NOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity NOR3; + +library ieee; +use ieee.std_logic_1164.all; + + entity NOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity NOR4; + +--########################## +--######## XOR GATES ####### +--########################## +library ieee; +use ieee.std_logic_1164.all; + + entity XOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity XOR2; + +library ieee; +use ieee.std_logic_1164.all; + + entity XOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity XOR3; + +library ieee; +use ieee.std_logic_1164.all; + + entity XOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity XOR4; + +--########################## +--######## XNOR GATES ###### +--########################## +library ieee; +use ieee.std_logic_1164.all; + + entity XNOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end entity XNOR2; + +library ieee; +use ieee.std_logic_1164.all; + + entity XNOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end entity XNOR3; + +library ieee; +use ieee.std_logic_1164.all; + + entity XNOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end entity XNOR4; diff --git a/Task1/IEEE_1164_Gates_beh.vhdl b/Task1/IEEE_1164_Gates_beh.vhdl new file mode 100644 index 0000000..68c5d4f --- /dev/null +++ b/Task1/IEEE_1164_Gates_beh.vhdl @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; + +--########################## +--######## AND GATES ####### +--########################## +architecture behavior of AND2 is +begin + O<= I1 and I2; +end architecture behavior; + +architecture behavior of AND3 is +begin + O<= I1 and I2 and I3; +end architecture behavior; + +architecture behavior of AND4 is +begin + O<= I1 and I2 and I3 and I4; +end architecture behavior; + +--########################## +--######## NAND GATES ###### +--########################## +architecture behavior of NAND2 is +begin + O<= not(I1 and I2); +end architecture behavior; + +architecture behavior of NAND3 is +begin + O<= not(I1 and I2 and I3); +end architecture behavior; + +architecture behavior of NAND4 is +begin + O<= not(I1 and I2 and I3 and I4); +end architecture behavior; + +--########################## +--######## OR GATES ######## +--########################## +architecture behavior of OR2 is +begin + O<= I1 or I2; +end architecture behavior; + +architecture behavior of OR3 is +begin + O<= I1 or I2 or I3; +end architecture behavior; + +architecture behavior of OR4 is +begin + O<= I1 or I2 or I3 or I4; +end architecture behavior; + +--########################## +--######## NOR GATES ####### +--########################## +architecture behavior of NOR2 is +begin + O<= not(I1 or I2); +end architecture behavior; + +architecture behavior of NOR3 is +begin + O<= not(I1 or I2 or I3); +end architecture behavior; + +architecture behavior of NOR4 is +begin + O<= not(I1 or I2 or I3 or I4); +end architecture behavior; + +--########################## +--######## XOR GATES ####### +--########################## +architecture behavior of XOR2 is +begin + O<= I1 xor I2; +end architecture behavior; + +architecture behavior of XOR3 is +begin + O<= I1 xor I2 xor I3; +end architecture behavior; + +architecture behavior of XOR4 is +begin + O<= I1 xor I2 xor I3 xor I4; +end architecture behavior; + +--########################## +--######## XNOR GATES ###### +--########################## + +architecture behavior of XNOR2 is +begin + O<= not(I1 xor I2); +end architecture behavior; + +architecture behavior of XNOR3 is +begin + O<= not(I1 xor I2 xor I3); +end architecture behavior; + +architecture behavior of XNOR4 is +begin + O<= not(I1 xor I2 xor I3 xor I4); +end architecture behavior; diff --git a/Task1/IEEE_1164_Gates_pkg.vhdl b/Task1/IEEE_1164_Gates_pkg.vhdl new file mode 100644 index 0000000..8c79a8a --- /dev/null +++ b/Task1/IEEE_1164_Gates_pkg.vhdl @@ -0,0 +1,205 @@ +library ieee; +use ieee.std_logic_1164.all; + +package IEEE_1164_Gates_pkg is + +--########################## +--######## AND GATES ####### +--########################## + component AND2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component AND2; + + component AND3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component AND3; + + component AND4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component AND4; + +--########################## +--######## NAND GATES ###### +--########################## + component NAND2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component NAND2; + + component NAND3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component NAND3; + + component NAND4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component NAND4; + +--########################## +--######## OR GATES ######## +--########################## + component OR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component OR2; + + component OR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component OR3; + + component OR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component OR4; + +--########################## +--######## NOR GATES ####### +--########################## + component NOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component NOR2; + + component NOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component NOR3; + + component NOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component NOR4; + +--########################## +--######## XOR GATES ####### +--########################## + component XOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component XOR2; + + component XOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component XOR3; + + component XOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component XOR4; + +--########################## +--######## XNOR GATES ###### +--########################## + component XNOR2 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + O :out std_logic + ); + end component XNOR2; + + component XNOR3 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + O :out std_logic + ); + end component XNOR3; + + component XNOR4 is + port + ( + I1 :in std_logic; + I2 :in std_logic; + I3 :in std_logic; + I4 :in std_logic; + O :out std_logic + ); + end component XNOR4; + + +end IEEE_1164_Gates_pkg; diff --git a/Task1/Task1.ghw b/Task1/Task1.ghw new file mode 100644 index 0000000..3edb74b Binary files /dev/null and b/Task1/Task1.ghw differ diff --git a/Task1/Task1.vhdpproj b/Task1/Task1.vhdpproj new file mode 100644 index 0000000..8e7aba2 --- /dev/null +++ b/Task1/Task1.vhdpproj @@ -0,0 +1,13 @@ + + + + + + + + + + + Task1.vhd + + \ No newline at end of file diff --git a/Task1/desc_7_Task1.pdf b/Task1/desc_7_Task1.pdf new file mode 100644 index 0000000..57673b4 Binary files /dev/null and b/Task1/desc_7_Task1.pdf differ diff --git a/Task1/gates.vhdl b/Task1/gates.vhdl new file mode 100644 index 0000000..b06fd2a --- /dev/null +++ b/Task1/gates.vhdl @@ -0,0 +1,7 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity gates is + port( A,B,C,D : in std_logic; + O : out std_logic); +end gates; diff --git a/Task1/gates_beh.vhdl b/Task1/gates_beh.vhdl new file mode 100644 index 0000000..9d6bb48 --- /dev/null +++ b/Task1/gates_beh.vhdl @@ -0,0 +1,43 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use work.IEEE_1164_Gates_pkg.all; + +architecture behavior of gates is + + signal sig_g0, sig_g1, sig_g2, sig_g3 : std_logic; + +begin + + + G3: OR3 port map( + I1 => A, + I2 => not(B), + I3 => C, + O => sig_g3); + + G2: XOR3 port map( + I1 => not(B), + I2 => C, + I3 => not(D), + O => sig_g2); + + G1: OR3 port map( + I1 => A, + I2 => C, + I3 => not(D), + O => sig_g1); + + G0: AND3 port map( + I1 => not(A), + I2 => B, + I3 => C, + O => sig_g0); + + G4: OR4 port map( + I1 => sig_g3, + I2 => not(sig_g2), + I3 => sig_g1, + I4 => sig_g0, + O => O); + +end behavior; diff --git a/Task1/vhdl_ls.toml b/Task1/vhdl_ls.toml new file mode 100644 index 0000000..52b47f4 --- /dev/null +++ b/Task1/vhdl_ls.toml @@ -0,0 +1,18 @@ +# auto-generated +[Libraries] +work.files = [ + 'IEEE_1164_Gates.vhdl', + 'IEEE_1164_Gates_beh.vhdl', + 'IEEE_1164_Gates_pkg.vhdl', + 'gates.vhdl', + 'gates_beh.vhdl' +] +[libraries.work] +files = [ + 'IEEE_1164_Gates.vhdl', + 'IEEE_1164_Gates_beh.vhdl', + 'IEEE_1164_Gates_pkg.vhdl', + 'gates.vhdl', + 'gates_beh.vhdl' +] +# auto-generated-end \ No newline at end of file diff --git a/Task2/.gitignore b/Task2/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task2/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task2/Task2.vhdpproj b/Task2/Task2.vhdpproj new file mode 100644 index 0000000..c622866 --- /dev/null +++ b/Task2/Task2.vhdpproj @@ -0,0 +1,10 @@ + + + + + + + + Task2.vhd + + \ No newline at end of file diff --git a/Task2/demux.vhdl b/Task2/demux.vhdl new file mode 100644 index 0000000..7fff75b --- /dev/null +++ b/Task2/demux.vhdl @@ -0,0 +1,13 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity demux is + port ( IN1 : in std_logic_vector((4 - 1) downto 0); + SEL : in std_logic_vector((3 - 1) downto 0); + OUT1 : out std_logic_vector((4 - 1) downto 0); + OUT2 : out std_logic_vector((4 - 1) downto 0); + OUT3 : out std_logic_vector((4 - 1) downto 0); + OUT4 : out std_logic_vector((4 - 1) downto 0); + OUT5 : out std_logic_vector((4 - 1) downto 0)); + +end demux; \ No newline at end of file diff --git a/Task2/demux_beh.vhdl b/Task2/demux_beh.vhdl new file mode 100644 index 0000000..47d58b8 --- /dev/null +++ b/Task2/demux_beh.vhdl @@ -0,0 +1,56 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +architecture behavior of demux is + + CONSTANT O1 : std_logic_vector(0 to 2) := "000"; + CONSTANT O2 : std_logic_vector(0 to 2) := "001"; + CONSTANT O3 : std_logic_vector(0 to 2) := "010"; + CONSTANT O4 : std_logic_vector(0 to 2) := "011"; + CONSTANT O5 : std_logic_vector(0 to 2) := "100"; + CONSTANT OE : std_logic_vector(0 to 3) := "0000"; + +begin + process(SEL, IN1) + begin + case SEL is + when O1 => + OUT1 <= IN1; + OUT2 <= OE; + OUT3 <= OE; + OUT4 <= OE; + OUT5 <= OE; + when O2 => + OUT1 <= OE; + OUT2 <= IN1; + OUT3 <= OE; + OUT4 <= OE; + OUT5 <= OE; + when O3 => OUT3 <= IN1; + OUT1 <= OE; + OUT2 <= OE; + OUT3 <= IN1; + OUT4 <= OE; + OUT5 <= OE; + when O4 => OUT4 <= IN1; + OUT1 <= OE; + OUT2 <= OE; + OUT3 <= OE; + OUT4 <= IN1; + OUT5 <= OE; + when O5 => OUT5 <= IN1; + OUT1 <= OE; + OUT2 <= OE; + OUT3 <= OE; + OUT4 <= OE; + OUT5 <= IN1; + when others => + OUT1 <= OE; + OUT2 <= OE; + OUT3 <= OE; + OUT4 <= OE; + OUT5 <= OE; + end case; + end process; +end behavior; \ No newline at end of file diff --git a/Task2/desc_7_Task2.pdf b/Task2/desc_7_Task2.pdf new file mode 100644 index 0000000..7ae46be Binary files /dev/null and b/Task2/desc_7_Task2.pdf differ diff --git a/Task2/vhdl_ls.toml b/Task2/vhdl_ls.toml new file mode 100644 index 0000000..cb987b3 --- /dev/null +++ b/Task2/vhdl_ls.toml @@ -0,0 +1,12 @@ +# auto-generated +[Libraries] +work.files = [ + 'Task2.vhd', + 'Task2_tb.vhd' +] +[libraries.work] +files = [ + 'Task2.vhd', + 'Task2_tb.vhd' +] +# auto-generated-end \ No newline at end of file diff --git a/Task3/.gitignore b/Task3/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task3/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task3/Task3.vhdpproj b/Task3/Task3.vhdpproj new file mode 100644 index 0000000..98a6a3b --- /dev/null +++ b/Task3/Task3.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/Task3/counter.vhdl b/Task3/counter.vhdl new file mode 100644 index 0000000..5db2d12 --- /dev/null +++ b/Task3/counter.vhdl @@ -0,0 +1,15 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity counter is + port( + CLK : in std_logic; + RST : in std_logic; + Enable : in std_logic; + SyncLoadInput : in std_logic; + AsyncClear : in std_logic; + Input : in std_logic_vector((6-1) downto 0); + Output : out std_logic_vector((6-1) downto 0) + ); +end counter; \ No newline at end of file diff --git a/Task3/counter_beh.vhdl b/Task3/counter_beh.vhdl new file mode 100644 index 0000000..4a9e1ca --- /dev/null +++ b/Task3/counter_beh.vhdl @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +architecture behavioral of counter is + +begin + process(CLK, RST, AsyncClear) + begin + if AsyncClear = '1' then + Output <= "000000"; -- Asynchrones Löschen + elsif rising_edge(CLK) then + if RST = '1' then + Output <= "000000"; -- Synchroner Reset + elsif Enable = '1' then + if SyncLoadInput = '1' then + Output <= Input; -- Synchrones Laden + else + Output <= std_logic_vector(unsigned(Output) + 1); -- Inkrement + end if; + end if; + end if; + end process; +end behavioral; \ No newline at end of file diff --git a/Task3/desc_7_Task3.pdf b/Task3/desc_7_Task3.pdf new file mode 100644 index 0000000..e569f1d Binary files /dev/null and b/Task3/desc_7_Task3.pdf differ diff --git a/Task3/vhdl_ls.toml b/Task3/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task3/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task4/.gitignore b/Task4/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task4/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task4/Task4.vhdpproj b/Task4/Task4.vhdpproj new file mode 100644 index 0000000..71ecc5d --- /dev/null +++ b/Task4/Task4.vhdpproj @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/Task4/desc_7_Task4.pdf b/Task4/desc_7_Task4.pdf new file mode 100644 index 0000000..6bab34d Binary files /dev/null and b/Task4/desc_7_Task4.pdf differ diff --git a/Task4/fsm.vhdl b/Task4/fsm.vhdl new file mode 100644 index 0000000..c7a6c9c --- /dev/null +++ b/Task4/fsm.vhdl @@ -0,0 +1,13 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use work.fsm_pkg.all; + +entity fsm is + port( + CLK : in std_logic; + INPUT : in std_logic_vector(1 downto 0); + RST : in std_logic; + OUTPUT : out std_logic_vector(1 downto 0); + STATE : out fsm_state + ); +end fsm; diff --git a/Task4/fsm_beh.vhdl b/Task4/fsm_beh.vhdl new file mode 100644 index 0000000..6651a50 --- /dev/null +++ b/Task4/fsm_beh.vhdl @@ -0,0 +1,93 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use work.fsm_pkg.all; + +architecture behavior of fsm is + + signal current_state, next_state : work.fsm_pkg.fsm_state; + signal next_output : std_logic_vector(1 downto 0); + +begin + + process(CLK, RST) + begin + if rising_edge(CLK) then + if RST = '1' then + current_state <= START; + OUTPUT <= "00"; + else + current_state <= next_state; + OUTPUT <= next_output; + end if; + end if; + end process; + + process(current_state, INPUT) + begin + case current_state is + when START => + if INPUT = "11" then + next_state <= S2; + next_output <= "00"; + + else + next_state <= START; + next_output <= "00"; + + end if; + + when S0 => + if INPUT = "00" then + next_state <= S2; + next_output <= "00"; + + elsif INPUT = "10" then + next_state <= S0; + next_output <= "11"; + + else + next_state <= S0; + next_output <= "00"; + + end if; + + when S1 => + if INPUT = "00" then + next_state <= S1; + next_output <= "00"; + + elsif INPUT = "10" then + next_state <= S2; + next_output <= "10"; + + else + next_state <= S1; + next_output <= "00"; + + end if; + + when S2 => + if INPUT = "00" then + next_state <= S0; + next_output <= "01"; + + elsif INPUT = "01" then + next_state <= S1; + next_output <= "10"; + + elsif INPUT = "10" then + next_state <= S2; + next_output <= "11"; + + else + next_state <= S2; + next_output <= "00"; + + end if; + + end case; + end process; + + STATE <= current_state; + +end behavior; \ No newline at end of file diff --git a/Task4/fsm_pkg.vhdl b/Task4/fsm_pkg.vhdl new file mode 100644 index 0000000..1543771 --- /dev/null +++ b/Task4/fsm_pkg.vhdl @@ -0,0 +1,9 @@ +package fsm_pkg is + type fsm_state is + ( + START, + S0, + S1, + S2 + ); +end package fsm_pkg; \ No newline at end of file diff --git a/Task4/vhdl_ls.toml b/Task4/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task4/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task5/.gitignore b/Task5/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task5/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task5/RAM.vhdl b/Task5/RAM.vhdl new file mode 100644 index 0000000..8d54a1c --- /dev/null +++ b/Task5/RAM.vhdl @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity RAM is + port( Clk : in std_logic; + addr1 : in std_logic_vector(6 downto 0); + addr2 : in std_logic_vector(6 downto 0); + en_read1 : in std_logic; + en_read2 : in std_logic; + en_write : in std_logic; + input : in std_logic_vector(17 downto 0); + output1 : out std_logic_vector(35 downto 0); + output2 : out std_logic_vector(35 downto 0) + ); +end RAM; diff --git a/Task5/RAM_beh.vhdl b/Task5/RAM_beh.vhdl new file mode 100644 index 0000000..e7fabf1 --- /dev/null +++ b/Task5/RAM_beh.vhdl @@ -0,0 +1,60 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.Numeric_Std.all; + +architecture Behavioral of RAM is + -- Die Länge der Adressen beträgt 6 Bit -> Länge/Größe des Vektors 64 + -- die Länge der einzelnen Speicherzellen 8 Bit + type memory_type is array (0 to 127) of std_logic_vector(17 downto 0); + -- Der anfängliche Inhalt des Speichers ist Null. + signal memory : memory_type := (others => (others => '0')); + --constant for high Z + constant high_z : std_logic_vector(35 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + +begin + + process (Clk) is + variable addr1_int : INTEGER; + variable addr2_int : INTEGER; + begin + if rising_edge(Clk) then + + output1 <= high_z; + output2 <= high_z; + + addr1_int := to_integer(UNSIGNED(addr1)); + addr2_int := to_integer(UNSIGNED(addr2)); + + if en_write = '0' then + -- lesen + if en_read1 = '1' then + output1 <= memory(addr1_int+1) & memory(addr1_int); + end if; + if en_read2 = '1' then + output2 <= memory(addr2_int+1) & memory(addr2_int); + end if; + + --high Z wenn nur eins gelesen wird: + if (en_read2 = '0') and (en_read1 = '1') then + output2 <= high_z; + elsif (en_read1 = '0') and (en_read2 = '1') then + output1 <= high_z; + end if; + end if; + + -- schreiben + if (en_write = '1') and (en_read1 = '0') and (en_read2 = '0') then + memory(addr1_int) <= input; + + -- schreiben und lesen von addr2 + elsif (en_write = '1') and (en_read1 = '0') and (en_read2 = '1') then + --kann nur ausgeführ werden wenn addr1 != addr2 + if not(addr1_int = addr2_int) and not(addr1_int = addr2_int+1) then + memory(addr1_int) <= input; + output2 <= memory(addr2_int+1) & memory(addr2_int); + end if; + + end if; + end if; + end process; +end Behavioral; \ No newline at end of file diff --git a/Task5/Task5.vhdpproj b/Task5/Task5.vhdpproj new file mode 100644 index 0000000..382b43f --- /dev/null +++ b/Task5/Task5.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/Task5/desc_7_Task5.pdf b/Task5/desc_7_Task5.pdf new file mode 100644 index 0000000..10abb7d Binary files /dev/null and b/Task5/desc_7_Task5.pdf differ diff --git a/Task5/vhdl_ls.toml b/Task5/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task5/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task6/Task6.vhdpproj b/Task6/Task6.vhdpproj new file mode 100644 index 0000000..1354a2d --- /dev/null +++ b/Task6/Task6.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/Task6/cache.vhdl b/Task6/cache.vhdl new file mode 100644 index 0000000..24d6243 --- /dev/null +++ b/Task6/cache.vhdl @@ -0,0 +1,13 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity cache is + port( + addr : in std_logic_vector(8-1 downto 0); + clk : in std_logic; + en_read : in std_logic; + data : out std_logic_vector(7-1 downto 0); + ch_cm : out std_logic + ); +end cache; \ No newline at end of file diff --git a/Task6/cache_beh.vhdl b/Task6/cache_beh.vhdl new file mode 100644 index 0000000..2bf04f0 --- /dev/null +++ b/Task6/cache_beh.vhdl @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +architecture behavioral of cache is + -- Cache parameters + constant CACHE_SIZE : integer := 16; + constant TAG_WIDTH : integer := 4; + constant DATA_WIDTH : integer := 7; + constant INDEX_WIDTH : integer := 4; + + -- Cache memory + type cache_array is array (0 to CACHE_SIZE-1) of std_logic_vector(TAG_WIDTH+DATA_WIDTH-1 downto 0); + constant cache_content : cache_array := ( + "10001100010", "10000111101", "00111010011", "11001000110", + "10001101111", "10001110110", "11011100001", "10111101011", + "11101101110", "10001111110", "11010001110", "11011000011", + "11111100000", "10101001001", "10000101011", "11101010100" + ); + + -- Signals + signal data_next : std_logic_vector(6 downto 0); + signal hit_next : std_logic; + +begin + process(clk) + begin + if falling_edge(clk) then + if en_read = '1' then + data <= data_next; + ch_cm <= hit_next; + else + data <= "ZZZZZZZ"; + ch_cm <= '0'; + end if; + end if; + end process; + + process(addr,clk) + + variable index : integer range 0 to CACHE_SIZE-1; + variable tag : std_logic_vector(TAG_WIDTH-1 downto 0); + variable cache_tag : std_logic_vector(TAG_WIDTH-1 downto 0); + variable cache_data : std_logic_vector(DATA_WIDTH-1 downto 0); + + begin + -- Extract index and tag from address + index := to_integer(unsigned(addr(INDEX_WIDTH-1 downto 0))); + tag := addr(addr'length-1 downto INDEX_WIDTH); + + cache_tag := cache_content(index)(TAG_WIDTH+DATA_WIDTH-1 downto DATA_WIDTH); + cache_data := cache_content(index)(DATA_WIDTH-1 downto 0); + + if tag = cache_tag then + hit_next <= '1'; -- Cache hit + data_next <= cache_data; + else + hit_next <= '0'; + data_next <= (others => 'Z'); -- Cache miss + end if; + end process; + +end architecture behavioral; \ No newline at end of file diff --git a/Task6/desc_7_Task6.pdf b/Task6/desc_7_Task6.pdf new file mode 100644 index 0000000..cb00802 Binary files /dev/null and b/Task6/desc_7_Task6.pdf differ diff --git a/Task6/vhdl_ls.toml b/Task6/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task6/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task7/.gitignore b/Task7/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task7/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task7/Task7.vhdpproj b/Task7/Task7.vhdpproj new file mode 100644 index 0000000..c0f6e5e --- /dev/null +++ b/Task7/Task7.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/Task7/desc_7_Task7.pdf b/Task7/desc_7_Task7.pdf new file mode 100644 index 0000000..9028228 Binary files /dev/null and b/Task7/desc_7_Task7.pdf differ diff --git a/Task7/pwm.vhdl b/Task7/pwm.vhdl new file mode 100644 index 0000000..79239b1 --- /dev/null +++ b/Task7/pwm.vhdl @@ -0,0 +1,7 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity pwm is + port( CLK : in std_logic; + O : out std_logic); +end pwm; diff --git a/Task7/pwm_beh.vhdl b/Task7/pwm_beh.vhdl new file mode 100644 index 0000000..d7917ae --- /dev/null +++ b/Task7/pwm_beh.vhdl @@ -0,0 +1,40 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +architecture behavior of pwm is + + -- Constants for PWM parameters + constant CLK_PERIOD : time := 20 ns; -- Assuming 50 MHz clock + constant PWM_PERIOD : time := 10 us; -- Desired period of 10 microseconds + constant DUTY_CYCLE : time := 7.2 us; -- 72% of the period + + -- Signal to store the counter value + signal counter : natural range 0 to integer(PWM_PERIOD / CLK_PERIOD) - 1; + +begin + + -- Synchronous counter process + process(CLK) + begin + if rising_edge(CLK) then + if counter = integer(PWM_PERIOD / CLK_PERIOD) - 1 then + counter <= 0; + else + counter <= counter + 1; + end if; + end if; + end process; + + -- PWM output generation process + process(CLK, counter) + begin + if rising_edge(CLK) then + if (CLK_PERIOD * integer(counter)) < DUTY_CYCLE then + O <= '1'; + else + O <= '0'; + end if; + end if; + end process; + +end behavior; \ No newline at end of file diff --git a/Task7/vhdl_ls.toml b/Task7/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task7/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file diff --git a/Task8/.gitignore b/Task8/.gitignore new file mode 100644 index 0000000..2b04e7f --- /dev/null +++ b/Task8/.gitignore @@ -0,0 +1,40 @@ +## Default .gitignore for VHDPlus Projects + +## Ignore generated vhdl files, files generated by compiling with quartus +Generated/ +incremental_db/ +output_files/ +db/ + +## MacOS +.DS_Store + +## ModelSim +Modelsim/ + +## Quartus specific. +## *.qsf +## *.qpf + +## ISSP +Libraries/.qsys_edit + +## NIOS +*.map +*.objdump +*.elf +*.flash +*.sopcinfo + +## Clangd +.clangd/ +.cache/ +obj/ +mem_init/ + +## BSP Libraries +**/Software/**/generated_bsp/ +**/Software/**/compile_commands.json + +## Python +*__pycache__* \ No newline at end of file diff --git a/Task8/Task8.vhdpproj b/Task8/Task8.vhdpproj new file mode 100644 index 0000000..314e2e9 --- /dev/null +++ b/Task8/Task8.vhdpproj @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/Task8/arithmetic.vhdl b/Task8/arithmetic.vhdl new file mode 100644 index 0000000..8760487 --- /dev/null +++ b/Task8/arithmetic.vhdl @@ -0,0 +1,12 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity arithmetic is + port( I1 :in std_logic_vector(15-1 downto 0); -- Operand 1 + I2 :in std_logic_vector(12-1 downto 0); -- Operand 2 + O :out std_logic_vector(15-1 downto 0); -- Output + C :out std_logic; -- Carry Flag + V :out std_logic; -- Overflow Flag + VALID :out std_logic -- Flag to indicate if the solution is valid or not +); +end arithmetic; \ No newline at end of file diff --git a/Task8/arithmetic_beh.vhdl b/Task8/arithmetic_beh.vhdl new file mode 100644 index 0000000..1c1aa76 --- /dev/null +++ b/Task8/arithmetic_beh.vhdl @@ -0,0 +1,8 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +architecture behavior of arithmetic is + +begin + +end behavior; diff --git a/Task8/desc_7_Task8.pdf b/Task8/desc_7_Task8.pdf new file mode 100644 index 0000000..9c5cc18 Binary files /dev/null and b/Task8/desc_7_Task8.pdf differ diff --git a/Task8/vhdl_ls.toml b/Task8/vhdl_ls.toml new file mode 100644 index 0000000..807f235 --- /dev/null +++ b/Task8/vhdl_ls.toml @@ -0,0 +1,8 @@ +# auto-generated +[Libraries] +work.files = [ +] +[libraries.work] +files = [ +] +# auto-generated-end \ No newline at end of file