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me0nline
2025-02-10 20:28:13 +01:00
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Task1/.gitignore
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## Default .gitignore for VHDPlus Projects
## Ignore generated vhdl files, files generated by compiling with quartus
Generated/
incremental_db/
output_files/
db/
## MacOS
.DS_Store
## ModelSim
Modelsim/
## Quartus specific.
## *.qsf
## *.qpf
## ISSP
Libraries/.qsys_edit
## NIOS
*.map
*.objdump
*.elf
*.flash
*.sopcinfo
## Clangd
.clangd/
.cache/
obj/
mem_init/
## BSP Libraries
**/Software/**/generated_bsp/
**/Software/**/compile_commands.json
## Python
*__pycache__*
Task1/IEEE_1164_Gates.vhdl
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library ieee;
use ieee.std_logic_1164.all;
--##########################
--######## AND GATES #######
--##########################
entity AND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity AND2;
library ieee;
use ieee.std_logic_1164.all;
entity AND3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity AND3;
library ieee;
use ieee.std_logic_1164.all;
entity AND4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity AND4;
--##########################
--######## NAND GATES ######
--##########################
library ieee;
use ieee.std_logic_1164.all;
entity NAND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity NAND2;
library ieee;
use ieee.std_logic_1164.all;
entity NAND3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity NAND3;
library ieee;
use ieee.std_logic_1164.all;
entity NAND4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity NAND4;
--##########################
--######## OR GATES ########
--##########################
library ieee;
use ieee.std_logic_1164.all;
entity OR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity OR2;
library ieee;
use ieee.std_logic_1164.all;
entity OR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity OR3;
library ieee;
use ieee.std_logic_1164.all;
entity OR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity OR4;
--##########################
--######## NOR GATES #######
--##########################
library ieee;
use ieee.std_logic_1164.all;
entity NOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity NOR2;
library ieee;
use ieee.std_logic_1164.all;
entity NOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity NOR3;
library ieee;
use ieee.std_logic_1164.all;
entity NOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity NOR4;
--##########################
--######## XOR GATES #######
--##########################
library ieee;
use ieee.std_logic_1164.all;
entity XOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity XOR2;
library ieee;
use ieee.std_logic_1164.all;
entity XOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity XOR3;
library ieee;
use ieee.std_logic_1164.all;
entity XOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity XOR4;
--##########################
--######## XNOR GATES ######
--##########################
library ieee;
use ieee.std_logic_1164.all;
entity XNOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end entity XNOR2;
library ieee;
use ieee.std_logic_1164.all;
entity XNOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end entity XNOR3;
library ieee;
use ieee.std_logic_1164.all;
entity XNOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end entity XNOR4;
Task1/IEEE_1164_Gates_beh.vhdl
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library ieee;
use ieee.std_logic_1164.all;
--##########################
--######## AND GATES #######
--##########################
architecture behavior of AND2 is
begin
O<= I1 and I2;
end architecture behavior;
architecture behavior of AND3 is
begin
O<= I1 and I2 and I3;
end architecture behavior;
architecture behavior of AND4 is
begin
O<= I1 and I2 and I3 and I4;
end architecture behavior;
--##########################
--######## NAND GATES ######
--##########################
architecture behavior of NAND2 is
begin
O<= not(I1 and I2);
end architecture behavior;
architecture behavior of NAND3 is
begin
O<= not(I1 and I2 and I3);
end architecture behavior;
architecture behavior of NAND4 is
begin
O<= not(I1 and I2 and I3 and I4);
end architecture behavior;
--##########################
--######## OR GATES ########
--##########################
architecture behavior of OR2 is
begin
O<= I1 or I2;
end architecture behavior;
architecture behavior of OR3 is
begin
O<= I1 or I2 or I3;
end architecture behavior;
architecture behavior of OR4 is
begin
O<= I1 or I2 or I3 or I4;
end architecture behavior;
--##########################
--######## NOR GATES #######
--##########################
architecture behavior of NOR2 is
begin
O<= not(I1 or I2);
end architecture behavior;
architecture behavior of NOR3 is
begin
O<= not(I1 or I2 or I3);
end architecture behavior;
architecture behavior of NOR4 is
begin
O<= not(I1 or I2 or I3 or I4);
end architecture behavior;
--##########################
--######## XOR GATES #######
--##########################
architecture behavior of XOR2 is
begin
O<= I1 xor I2;
end architecture behavior;
architecture behavior of XOR3 is
begin
O<= I1 xor I2 xor I3;
end architecture behavior;
architecture behavior of XOR4 is
begin
O<= I1 xor I2 xor I3 xor I4;
end architecture behavior;
--##########################
--######## XNOR GATES ######
--##########################
architecture behavior of XNOR2 is
begin
O<= not(I1 xor I2);
end architecture behavior;
architecture behavior of XNOR3 is
begin
O<= not(I1 xor I2 xor I3);
end architecture behavior;
architecture behavior of XNOR4 is
begin
O<= not(I1 xor I2 xor I3 xor I4);
end architecture behavior;
Task1/IEEE_1164_Gates_pkg.vhdl
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library ieee;
use ieee.std_logic_1164.all;
package IEEE_1164_Gates_pkg is
--##########################
--######## AND GATES #######
--##########################
component AND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component AND2;
component AND3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component AND3;
component AND4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component AND4;
--##########################
--######## NAND GATES ######
--##########################
component NAND2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component NAND2;
component NAND3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component NAND3;
component NAND4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component NAND4;
--##########################
--######## OR GATES ########
--##########################
component OR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component OR2;
component OR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component OR3;
component OR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component OR4;
--##########################
--######## NOR GATES #######
--##########################
component NOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component NOR2;
component NOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component NOR3;
component NOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component NOR4;
--##########################
--######## XOR GATES #######
--##########################
component XOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component XOR2;
component XOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component XOR3;
component XOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component XOR4;
--##########################
--######## XNOR GATES ######
--##########################
component XNOR2 is
port
(
I1 :in std_logic;
I2 :in std_logic;
O :out std_logic
);
end component XNOR2;
component XNOR3 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
O :out std_logic
);
end component XNOR3;
component XNOR4 is
port
(
I1 :in std_logic;
I2 :in std_logic;
I3 :in std_logic;
I4 :in std_logic;
O :out std_logic
);
end component XNOR4;
end IEEE_1164_Gates_pkg;
Task1/Task1.ghw
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Task1/Task1.vhdpproj
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<Project>
<ItemGroup>
<File Include="IEEE_1164_Gates.vhdl" />
<File Include="IEEE_1164_Gates_beh.vhdl" />
<File Include="IEEE_1164_Gates_pkg.vhdl" />
<File Include="desc_7_Task1.pdf" />
<File Include="gates.vhdl" />
<File Include="gates_beh.vhdl" />
</ItemGroup>
<PropertyGroup>
<HardwareStartPath>Task1.vhd</HardwareStartPath>
</PropertyGroup>
</Project>
Task1/desc_7_Task1.pdf
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Task1/gates.vhdl
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library IEEE;
use IEEE.std_logic_1164.all;
entity gates is
port( A,B,C,D : in std_logic;
O : out std_logic);
end gates;
Task1/gates_beh.vhdl
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library IEEE;
use IEEE.std_logic_1164.all;
use work.IEEE_1164_Gates_pkg.all;
architecture behavior of gates is
signal sig_g0, sig_g1, sig_g2, sig_g3 : std_logic;
begin
G3: OR3 port map(
I1 => A,
I2 => not(B),
I3 => C,
O => sig_g3);
G2: XOR3 port map(
I1 => not(B),
I2 => C,
I3 => not(D),
O => sig_g2);
G1: OR3 port map(
I1 => A,
I2 => C,
I3 => not(D),
O => sig_g1);
G0: AND3 port map(
I1 => not(A),
I2 => B,
I3 => C,
O => sig_g0);
G4: OR4 port map(
I1 => sig_g3,
I2 => not(sig_g2),
I3 => sig_g1,
I4 => sig_g0,
O => O);
end behavior;
Task1/vhdl_ls.toml
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# auto-generated
[Libraries]
work.files = [
'IEEE_1164_Gates.vhdl',
'IEEE_1164_Gates_beh.vhdl',
'IEEE_1164_Gates_pkg.vhdl',
'gates.vhdl',
'gates_beh.vhdl'
]
[libraries.work]
files = [
'IEEE_1164_Gates.vhdl',
'IEEE_1164_Gates_beh.vhdl',
'IEEE_1164_Gates_pkg.vhdl',
'gates.vhdl',
'gates_beh.vhdl'
]
# auto-generated-end