206 lines
4.3 KiB
VHDL
206 lines
4.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package IEEE_1164_Gates_pkg is
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--##########################
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--######## AND GATES #######
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--##########################
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component AND2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component AND2;
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component AND3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component AND3;
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component AND4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component AND4;
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--##########################
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--######## NAND GATES ######
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--##########################
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component NAND2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component NAND2;
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component NAND3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component NAND3;
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component NAND4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component NAND4;
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--##########################
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--######## OR GATES ########
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--##########################
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component OR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component OR2;
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component OR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component OR3;
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component OR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component OR4;
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--##########################
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--######## NOR GATES #######
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--##########################
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component NOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component NOR2;
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component NOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component NOR3;
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component NOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component NOR4;
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--##########################
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--######## XOR GATES #######
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--##########################
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component XOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component XOR2;
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component XOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component XOR3;
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component XOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component XOR4;
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--##########################
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--######## XNOR GATES ######
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--##########################
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component XNOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end component XNOR2;
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component XNOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end component XNOR3;
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component XNOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end component XNOR4;
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end IEEE_1164_Gates_pkg;
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