253 lines
4.9 KiB
VHDL
253 lines
4.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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--##########################
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--######## AND GATES #######
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--##########################
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entity AND2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity AND2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity AND3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity AND3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity AND4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity AND4;
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--##########################
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--######## NAND GATES ######
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--##########################
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library ieee;
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use ieee.std_logic_1164.all;
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entity NAND2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity NAND2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity NAND3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity NAND3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity NAND4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity NAND4;
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--##########################
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--######## OR GATES ########
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--##########################
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library ieee;
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use ieee.std_logic_1164.all;
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entity OR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity OR2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity OR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity OR3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity OR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity OR4;
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--##########################
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--######## NOR GATES #######
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--##########################
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library ieee;
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use ieee.std_logic_1164.all;
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entity NOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity NOR2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity NOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity NOR3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity NOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity NOR4;
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--##########################
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--######## XOR GATES #######
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--##########################
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library ieee;
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use ieee.std_logic_1164.all;
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entity XOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity XOR2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity XOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity XOR3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity XOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity XOR4;
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--##########################
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--######## XNOR GATES ######
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--##########################
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library ieee;
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use ieee.std_logic_1164.all;
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entity XNOR2 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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O :out std_logic
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);
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end entity XNOR2;
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library ieee;
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use ieee.std_logic_1164.all;
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entity XNOR3 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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O :out std_logic
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);
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end entity XNOR3;
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library ieee;
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use ieee.std_logic_1164.all;
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entity XNOR4 is
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port
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(
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I1 :in std_logic;
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I2 :in std_logic;
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I3 :in std_logic;
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I4 :in std_logic;
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O :out std_logic
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);
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end entity XNOR4;
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