112 lines
2.3 KiB
VHDL
112 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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--##########################
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--######## AND GATES #######
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--##########################
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architecture behavior of AND2 is
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begin
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O<= I1 and I2;
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end architecture behavior;
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architecture behavior of AND3 is
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begin
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O<= I1 and I2 and I3;
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end architecture behavior;
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architecture behavior of AND4 is
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begin
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O<= I1 and I2 and I3 and I4;
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end architecture behavior;
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--##########################
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--######## NAND GATES ######
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--##########################
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architecture behavior of NAND2 is
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begin
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O<= not(I1 and I2);
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end architecture behavior;
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architecture behavior of NAND3 is
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begin
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O<= not(I1 and I2 and I3);
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end architecture behavior;
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architecture behavior of NAND4 is
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begin
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O<= not(I1 and I2 and I3 and I4);
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end architecture behavior;
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--##########################
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--######## OR GATES ########
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--##########################
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architecture behavior of OR2 is
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begin
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O<= I1 or I2;
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end architecture behavior;
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architecture behavior of OR3 is
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begin
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O<= I1 or I2 or I3;
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end architecture behavior;
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architecture behavior of OR4 is
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begin
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O<= I1 or I2 or I3 or I4;
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end architecture behavior;
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--##########################
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--######## NOR GATES #######
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--##########################
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architecture behavior of NOR2 is
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begin
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O<= not(I1 or I2);
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end architecture behavior;
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architecture behavior of NOR3 is
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begin
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O<= not(I1 or I2 or I3);
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end architecture behavior;
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architecture behavior of NOR4 is
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begin
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O<= not(I1 or I2 or I3 or I4);
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end architecture behavior;
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--##########################
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--######## XOR GATES #######
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--##########################
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architecture behavior of XOR2 is
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begin
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O<= I1 xor I2;
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end architecture behavior;
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architecture behavior of XOR3 is
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begin
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O<= I1 xor I2 xor I3;
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end architecture behavior;
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architecture behavior of XOR4 is
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begin
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O<= I1 xor I2 xor I3 xor I4;
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end architecture behavior;
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--##########################
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--######## XNOR GATES ######
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--##########################
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architecture behavior of XNOR2 is
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begin
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O<= not(I1 xor I2);
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end architecture behavior;
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architecture behavior of XNOR3 is
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begin
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O<= not(I1 xor I2 xor I3);
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end architecture behavior;
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architecture behavior of XNOR4 is
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begin
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O<= not(I1 xor I2 xor I3 xor I4);
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end architecture behavior;
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