first commit

17_syncROM_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

17_syncROM_Example/17_syncROM_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup>
+    <HardwareStartPath>testbench.vhd</HardwareStartPath>
+  </PropertyGroup>
+</Project>

17_syncROM_Example/clkgen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

17_syncROM_Example/design.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity single_port_rom is
+    port
+    (
+        addr    : in std_logic_vector(15 downto 0);
+        clk        : in std_logic;
+        q        : out std_logic_vector(7 downto 0)
+    );
+end single_port_rom;
+    
+architecture rtl of single_port_rom is
+
+    -- Build a 2-D array type for the RoM
+    subtype word_t is std_logic_vector(7 downto 0);
+    type memory_t is array(0 to 5) of word_t;
+        
+    constant romdata : memory_t := (
+     X"FF",                            -- data for address 0 in HEX notation
+     X"A5",                            -- data for address 1 in HEX notation
+     X"AA",
+     X"B6",
+     X"5C",
+     X"23"
+     );
+     
+         
+begin
+    
+    process(clk)
+    variable addr_to_read : integer;
+    begin
+        if(rising_edge(clk)) then
+         addr_to_read := to_integer(unsigned(addr));
+         if addr_to_read <= 5 then
+          q <= romdata(addr_to_read);
+         else
+          q <= "XXXXXXXX";
+         end if;
+        end if;
+    end process;
+        
+end rtl;

17_syncROM_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component single_port_rom is
+port
+	(
+		addr	: in std_logic_vector(15 downto 0);
+		clk		: in std_logic;
+		q		: out std_logic_vector(7 downto 0)
+	);
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk : std_logic;
+signal sig_addr : std_logic_vector(15 downto 0);
+signal sig_q : std_logic_vector(7 downto 0);
+
+
+begin  
+  DUT: single_port_rom port map(
+     clk => sig_clk,
+     addr => sig_addr,
+     q => sig_q
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+stim: process 
+begin
+sig_addr <= "0000000000000000";
+wait for 12 ns;
+sig_addr <= "0000000000000001";
+wait for 12 ns;
+sig_addr <= std_logic_vector(to_unsigned(10,16));
+wait;
+end process stim;
+
+
+end tb;

17_syncROM_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+	'clkgen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'clkgen.vhd',
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end