first commit

15_FSM_Mealy_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

15_FSM_Mealy_Example/15_FSM_Mealy_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="fsm_syn.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

15_FSM_Mealy_Example/clkgen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

15_FSM_Mealy_Example/fsm_syn.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FSM_sync is
+    port ( clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out_sync  : out STD_LOGIC);
+end FSM_sync;
+
+architecture beh of FSM_sync is
+
+  type state_t is (S_start,S_direct,S_invert);
+
+  signal state : state_t := S_start;
+  signal next_state : state_t := S_start;
+
+  signal dbg_state: std_logic_vector(1 downto 0); -- just for  debugging (we can't see type state_t in the waveform viewer)
+
+  signal next_data_out : std_logic := '0';
+
+begin
+
+  p_seq: process (clk)
+  begin
+   if (clk'event and clk ='1') then
+     state   <= next_state;
+     data_out_sync <= next_data_out;
+   end if;
+  end process p_seq;
+
+
+  p_comb: process (state,data_in,direct,invert)
+  begin
+   case state is
+           when S_start => if direct AND NOT invert then
+                           next_data_out <= data_in;
+                           next_state <= S_direct;
+                         elsif  invert AND NOT direct then
+                           next_data_out <= not data_in;
+                           next_state <= S_invert;
+                         else
+                           next_data_out <= '0';
+                           next_state <= S_start;
+                         end if;
+
+           when S_direct  => if direct and not invert then
+                             next_state <= S_direct;
+                             next_data_out <= data_in;                   
+                           else
+                             next_state <= S_start;
+                             next_data_out <= '0';
+                         end if;
+
+           when S_invert => if invert and not direct then
+                             next_state <= S_invert;
+                             next_data_out <= not data_in;                   
+                           else
+                             next_state <= S_start;
+                             next_data_out <= '0';
+                         end if;
+        end case;
+
+  end process p_comb;
+
+  -- just for debugging, we transform the state (type state_t) to a 2bit vector, which we can see in the waveform viewer
+  dbg: process (state)
+  begin
+   case state is
+           when S_start => dbg_state <= "00";                   
+           when S_direct  => dbg_state <= "01";
+           when S_invert  => dbg_state <= "10";
+        end case;
+  end process dbg;
+
+
+end beh;

15_FSM_Mealy_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component FSM is
+port (  clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out : out STD_LOGIC);
+end component;
+
+component FSM_sync is
+port (  clk : in  STD_LOGIC;
+           data_in : in  STD_LOGIC;
+           direct  : in  STD_LOGIC;
+           invert : in STD_LOGIC;
+           data_out_sync : out STD_LOGIC);
+end component;
+
+
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk, sig_din,sig_dout, sig_dout_sync, sig_direct, sig_invert : std_logic;
+
+
+begin  
+  DUT: FSM port map(
+     clk => sig_clk,
+     direct => sig_direct,
+     invert => sig_invert,
+     data_in => sig_din,
+     data_out => sig_dout
+   );
+   
+    DUT_sync: FSM_sync port map(
+     clk => sig_clk,
+     direct => sig_direct,
+     invert => sig_invert,
+     data_in => sig_din,
+     data_out_sync => sig_dout_sync
+   );
+   
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+sig_din <='0', '1' after 22 ns, '0' after 40 ns, '1' after 100 ns, '0' after 140 ns, '1' after 142 ns, '0' after 150 ns, '1' after 170 ns, '0' after 200 ns, '1' after 282 ns, '0' after 482 ns, '1' after 500 ns, '0' after 525 ns, '1' after 570 ns, '0' after 632ns, '1' after 750 ns;
+sig_direct<= '0',  '1' after 100 ns, '0' after 400 ns, '1' after 600 ns;
+sig_invert<= '0',  '1' after 350 ns, '0' after 650 ns, '1' after 700 ns;
+end tb;

15_FSM_Mealy_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end