first commit

02_Fulladder/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

02_Fulladder/02_Fulladder.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="fulladder.vhd" />
+    <File Include="halfadder.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

02_Fulladder/design.vhd

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+-- empty: NOT EVEN library (otherwise compiler error)

02_Fulladder/fulladder.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder is
+    port (afa_i :   in std_logic;
+        bfa_i :   in std_logic;
+        cinfa_i :   in std_logic;
+        sumfa_o : out std_logic;
+        coutfa_o :  out std_logic);
+end fulladder;
+
+architecture fa_behaviour of fulladder is
+
+-- Halfadder component
+    component halfadder is
+        port (a_i :   in std_logic;
+            b_i :   in std_logic;
+            sum_o : out std_logic;
+            cy_o :  out std_logic);
+    end component;
+
+    signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;
+
+begin
+
+-- Instances of two halfadders
+    HA1: halfadder port map(
+        a_i => afa_i,
+        b_i => bfa_i,
+        sum_o => sig_ha1e,
+        cy_o => sig_ha1c);
+    
+    HA2: halfadder port map(
+        a_i => sig_ha1e,
+        b_i => cinfa_i,
+        sum_o => sumfa_o,
+        cy_o => sig_ha2c);
+
+-- The OR gate
+    coutfa_o <= sig_ha1c OR sig_ha2c;
+    
+end fa_behaviour;

02_Fulladder/halfadder.vhd

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+-- The halfadder design
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity halfadder is
+    port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+architecture behavior of halfadder is
+begin
+    sum_o <= a_i xor b_i;
+    cy_o <= a_i and b_i;
+end behavior;

02_Fulladder/testbench.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+  -- DUT components
+    component fulladder is
+        port (afa_i :   in std_logic;
+            bfa_i :   in std_logic;
+            cinfa_i :   in std_logic;
+            sumfa_o : out std_logic;
+            coutfa_o :  out std_logic);
+    end component;
+
+    signal sig_afa, sig_bfa, sig_cinfa, sig_sumfa, sig_coutfa: std_logic;
+
+begin
+
+    -- Connect DUTs
+    DUT_s: fulladder port map(
+        afa_i => sig_afa,
+        bfa_i => sig_bfa,
+        cinfa_i => sig_cinfa,
+        sumfa_o => sig_sumfa,
+        coutfa_o => sig_coutfa);
+
+
+    sig_afa <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns,'0' after 400 ns, '1' after 500 ns, '0' after 600 ns, '1' after 700 ns;
+    sig_bfa <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 600 ns;
+    sig_cinfa <= '0', '1' after 400 ns;
+end tb;

02_Fulladder/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end