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me0nline
2025-02-10 20:28:13 +01:00
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20_pdRAM_Example/.gitignore
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## Default .gitignore for VHDPlus Projects
## Ignore generated vhdl files, files generated by compiling with quartus
Generated/
incremental_db/
output_files/
db/
## MacOS
.DS_Store
## ModelSim
Modelsim/
## Quartus specific.
## *.qsf
## *.qpf
## ISSP
Libraries/.qsys_edit
## NIOS
*.map
*.objdump
*.elf
*.flash
*.sopcinfo
## Clangd
.clangd/
.cache/
obj/
mem_init/
## BSP Libraries
**/Software/**/generated_bsp/
**/Software/**/compile_commands.json
## Python
*__pycache__*
20_pdRAM_Example/20_pdRAM_Example.vhdpproj
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<Project>
<ItemGroup>
<File Include="clkgen.vhd" />
<File Include="design.vhd" />
<File Include="testbench.vhd" />
</ItemGroup>
<PropertyGroup>
<HardwareStartPath>testbench.vhd</HardwareStartPath>
</PropertyGroup>
</Project>
20_pdRAM_Example/clkgen.vhd
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-- Clock Generator
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is
port (clk : out std_logic);
end clkGen;
architecture behavior of clkGen is
constant clk_period : time := 10 ns;
begin
clkgen : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process clkgen;
end behavior;
20_pdRAM_Example/design.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_dp is
port (
clk :in std_logic; -- Clock Input
address_0 :in std_logic_vector (8-1 downto 0); -- address_0 Input
data_0 :inout std_logic_vector (8-1 downto 0); -- data_0 bi-directional
cs_0 :in std_logic; -- Chip Select
we_0 :in std_logic; -- Write Enable/Read Enable
oe_0 :in std_logic; -- Output Enable
address_1 :in std_logic_vector (8-1 downto 0); -- address_1 Input
data_1 :inout std_logic_vector (8-1 downto 0); -- data_1 bi-directional
cs_1 :in std_logic; -- Chip Select
we_1 :in std_logic; -- Write Enable/Read Enable
oe_1 :in std_logic -- Output Enable
);
end entity;
architecture rtl of ram_dp is
----------------Internal variables----------------
constant RAM_DEPTH :integer := 2**8;
signal data_0_out :std_logic_vector (8-1 downto 0);
signal data_1_out :std_logic_vector (8-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (8-1 downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------
-- Memory Write Block (0 and 1)
MEM_WRITE:
process (clk) begin
if (rising_edge(clk)) then
if ( cs_0 = '1' and we_0 = '1') then
mem(conv_integer(address_0)) <= data_0;
elsif (cs_1 = '1' and we_1 = '1') then
mem(conv_integer(address_1)) <= data_1;
end if;
end if;
end process;
-- Memory Read Block 0
MEM_READ_0:
process (clk) begin
if (rising_edge(clk)) then
if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
data_0_out <= mem(conv_integer(address_0));
else
data_0_out <= (others=>'0');
end if;
end if;
end process;
-- Memory Read Block 1
MEM_READ_1:
process (clk) begin
if (rising_edge(clk)) then
if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
data_1_out <= mem(conv_integer(address_1));
else
data_1_out <= (others=>'0');
end if;
end if;
end process;
-- Tri-State Buffer control
-- output : When we_0 = 0, oe_0 = 1, cs_0 = 1
data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z');
--Second Port of RAM
-- output : When we_1 = 0, oe_1 = 1, cs_1 = 1
data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z');
end architecture;
20_pdRAM_Example/testbench.vhd
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-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component ram_dp is
port (
clk :in std_logic;
address_0 :in std_logic_vector (8-1 downto 0);
data_0 :inout std_logic_vector (8-1 downto 0);
cs_0 :in std_logic;
we_0 :in std_logic;
oe_0 :in std_logic;
address_1 :in std_logic_vector (8-1 downto 0);
data_1 :inout std_logic_vector (8-1 downto 0);
cs_1 :in std_logic;
we_1 :in std_logic;
oe_1 :in std_logic
);
end component;
component clkGen is
port (clk : out std_logic);
end component;
signal sig_clk : std_logic;
signal sig_address_0 : std_logic_vector (8-1 downto 0);
signal sig_data_0 : std_logic_vector (8-1 downto 0);
signal sig_cs_0 : std_logic;
signal sig_we_0 : std_logic;
signal sig_oe_0 : std_logic;
signal sig_address_1 : std_logic_vector (8-1 downto 0);
signal sig_data_1 : std_logic_vector (8-1 downto 0);
signal sig_cs_1 : std_logic;
signal sig_we_1 : std_logic;
signal sig_oe_1 : std_logic;
begin
DUT: ram_dp port map(
clk => sig_clk,
address_0 => sig_address_0,
data_0 => sig_data_0,
cs_0 => sig_cs_0,
we_0 => sig_we_0,
oe_0 => sig_oe_0,
address_1 => sig_address_1,
data_1 => sig_data_1,
cs_1 => sig_cs_1,
we_1 => sig_we_1,
oe_1 => sig_oe_1
);
mClkGen : clkGen port map(
clk => sig_clk
);
stim: process
begin
sig_address_0 <= "00000000";
sig_data_0 <= "00000000";
sig_cs_0 <= '0';
sig_we_0 <= '0';
sig_oe_0 <= '0';
sig_address_1 <="00000000";
sig_data_1 <= "00000000";
sig_cs_1 <= '0';
sig_we_1 <= '0';
sig_oe_1 <= '0';
wait;
end process stim;
end tb;
20_pdRAM_Example/vhdl_ls.toml
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# auto-generated
[Libraries]
work.files = [
]
[libraries.work]
files = [
]
# auto-generated-end