82 lines
2.8 KiB
VHDL
82 lines
2.8 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity ram_dp is
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port (
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clk :in std_logic; -- Clock Input
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address_0 :in std_logic_vector (8-1 downto 0); -- address_0 Input
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data_0 :inout std_logic_vector (8-1 downto 0); -- data_0 bi-directional
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cs_0 :in std_logic; -- Chip Select
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we_0 :in std_logic; -- Write Enable/Read Enable
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oe_0 :in std_logic; -- Output Enable
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address_1 :in std_logic_vector (8-1 downto 0); -- address_1 Input
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data_1 :inout std_logic_vector (8-1 downto 0); -- data_1 bi-directional
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cs_1 :in std_logic; -- Chip Select
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we_1 :in std_logic; -- Write Enable/Read Enable
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oe_1 :in std_logic -- Output Enable
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);
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end entity;
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architecture rtl of ram_dp is
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----------------Internal variables----------------
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constant RAM_DEPTH :integer := 2**8;
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signal data_0_out :std_logic_vector (8-1 downto 0);
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signal data_1_out :std_logic_vector (8-1 downto 0);
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type RAM is array (integer range <>)of std_logic_vector (8-1 downto 0);
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signal mem : RAM (0 to RAM_DEPTH-1);
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begin
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----------------Code Starts Here------------------
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-- Memory Write Block (0 and 1)
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MEM_WRITE:
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process (clk) begin
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if (rising_edge(clk)) then
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if ( cs_0 = '1' and we_0 = '1') then
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mem(conv_integer(address_0)) <= data_0;
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elsif (cs_1 = '1' and we_1 = '1') then
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mem(conv_integer(address_1)) <= data_1;
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end if;
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end if;
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end process;
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-- Memory Read Block 0
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MEM_READ_0:
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process (clk) begin
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if (rising_edge(clk)) then
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if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
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data_0_out <= mem(conv_integer(address_0));
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else
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data_0_out <= (others=>'0');
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end if;
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end if;
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end process;
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-- Memory Read Block 1
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MEM_READ_1:
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process (clk) begin
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if (rising_edge(clk)) then
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if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
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data_1_out <= mem(conv_integer(address_1));
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else
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data_1_out <= (others=>'0');
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end if;
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end if;
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end process;
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-- Tri-State Buffer control
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-- output : When we_0 = 0, oe_0 = 1, cs_0 = 1
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data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z');
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--Second Port of RAM
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-- output : When we_1 = 0, oe_1 = 1, cs_1 = 1
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data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z');
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end architecture;
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