first commit

14_FSM_Moore_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

14_FSM_Moore_Example/14_FSM_Moore_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

14_FSM_Moore_Example/clkgen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

14_FSM_Moore_Example/design.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity FSM is
+    port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           start : in  STD_LOGIC;
+           stop  : in  STD_LOGIC;
+           cout  : out  STD_LOGIC_VECTOR (2 downto 0));
+end FSM;
+
+architecture beh of FSM is
+
+type state_t is (cs_reset,cs_wait,cs_one,cs_two,cs_three,cs_four,cs_five);
+signal state, next_state : state_t := cs_reset;
+
+
+begin
+
+p_seq: process (clk,reset)
+begin
+ if reset ='1' then
+   state <= cs_reset;
+ elsif (Clk'event and Clk ='1') then
+   state   <= next_state;
+ end if;
+end process p_seq;
+
+p_comb: process (state,start,stop)
+begin
+ case state is
+         when cs_reset => next_state <= cs_wait;
+                          cout <= "XXX";
+                      
+         when cs_wait  => if (start='1' and stop='0') then
+                           next_state <= cs_one;
+                          else
+                           next_state <= cs_wait;
+                          end if;
+                          cout <= "000";
+        
+         when cs_one  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_two;
+                         end if;
+                         cout <= "001";
+                      
+
+         when cs_two  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_three;
+                         end if;
+                         cout <= "010";
+                         
+         when cs_three  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_four;
+                         end if;
+                         cout <= "011";
+                         
+         when cs_four  => if (stop='1') then
+                          next_state <= cs_wait;
+                         else
+                          next_state <= cs_five;
+                         end if;
+                         cout <= "100";
+         
+         when cs_five  => next_state <= cs_wait;
+                          cout <= "101";
+                                               
+      end case;
+      
+end process p_comb;
+
+
+
+end beh;

14_FSM_Moore_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component FSM is
+port ( clk : in  STD_LOGIC;
+           reset : in  STD_LOGIC;
+           start : in  STD_LOGIC;
+           stop  : in  STD_LOGIC;
+           cout  : out  STD_LOGIC_VECTOR (2 downto 0));
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal sig_clk, sig_reset, sig_start, sig_stop : std_logic;
+signal sig_cout : STD_LOGIC_VECTOR (2 downto 0);
+
+begin  
+  DUT: FSM port map(
+     clk => sig_clk,
+     reset => sig_reset,
+     start => sig_start,
+     stop => sig_stop,
+     cout => sig_cout
+   );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+  
+
+
+sig_start <= '0', '1' after 22 ns, '0' after 45 ns, '1' after 82 ns, '0' after 86 ns;
+
+sig_reset <='0','1' after 102 ns, '0' after 123 ns;
+sig_stop <= '0', '1' after 58 ns, '0' after 68 ns;
+end tb;

14_FSM_Moore_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end