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10_LFSR_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

10_LFSR_Example/10_LFSR_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="clkgen.vhd" />
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

10_LFSR_Example/clkgen.vhd

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+-- Clock Generator
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity clkGen is
+  port (clk : out std_logic);
+end clkGen;
+
+architecture behavior of clkGen is
+
+constant clk_period : time := 10 ns;
+
+begin
+  clkgen : process
+  
+  begin
+  
+  	clk <= '0';
+    wait for clk_period/2;  
+    clk <= '1';
+    wait for clk_period/2;  
+  end process clkgen;
+end behavior;

10_LFSR_Example/design.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity LFSR is
+    Port ( clk     : in  std_logic;
+           value32 : out  std_logic_vector (31 downto 0);
+           value16 : out  std_logic_vector (15 downto 0);
+           value8  : out  std_logic_vector ( 7 downto 0));
+end LFSR;
+
+architecture Behavioral of LFSR is
+signal rnd32 : std_logic_vector (31 downto 0) := (others=>'0');
+signal rnd16 : std_logic_vector (15 downto 0) := (others=>'0');
+signal rnd8  : std_logic_vector ( 7 downto 0) := (others=>'0');
+begin
+   process begin
+      wait until rising_edge(CLK);
+       -- 8Bit
+       rnd8(7 downto 1) <= rnd8(6 downto 0) ;
+       rnd8(0) <= not(rnd8(7) XOR rnd8(6) XOR rnd8(4));
+       -- 16Bit
+       rnd16(15 downto 1) <= rnd16(14 downto 0) ;
+       rnd16(0) <= not(rnd16(15) XOR rnd16(14) XOR rnd16(13) XOR rnd16(4));
+       -- 32 Bit
+       rnd32(31 downto 1) <= rnd32(30 downto 0) ;
+       rnd32(0) <= not(rnd32(31) XOR rnd32(22) XOR rnd32(2) XOR rnd32(1));
+   end process;
+   value32 <= rnd32;
+   value16 <= rnd16;
+   value8  <= rnd8;
+end Behavioral;

10_LFSR_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+end testbench;
+
+architecture tb of testbench is
+
+component LFSR is
+Port ( clk     : in  std_logic;
+       value32 : out  std_logic_vector (31 downto 0);
+       value16 : out  std_logic_vector (15 downto 0);
+       value8  : out  std_logic_vector ( 7 downto 0));
+end component;
+
+component clkGen is
+  port (clk : out std_logic);
+end component;
+
+signal  sig_clk : std_logic;
+signal sig_r8 : std_logic_vector (7 downto 0);
+signal sig_r16 : std_logic_vector (15 downto 0);
+signal sig_r32 : std_logic_vector (31 downto 0);
+
+begin  
+  DUT: LFSR port map(
+     clk => sig_clk,
+     value32 => sig_r32,
+     value16 => sig_r16,
+     value8 => sig_r8
+  );
+  
+  mClkGen : clkGen port map(
+  	clk => sig_clk
+  );
+
+
+end tb;

10_LFSR_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end