first commit

07_DTime_GateDelay_Example/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

07_DTime_GateDelay_Example/07_DTime_GateDelay_Example.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

07_DTime_GateDelay_Example/design.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity log is
+  port (inp :   in std_logic;
+        C :   out std_logic);
+end log;
+
+architecture behavior of log is
+signal A,B : std_logic;
+begin
+  A <= NOT inp after 1 ns;
+  B <= A NAND '1' after 1 ns;
+  C <= A AND B after 1 ns;
+end behavior;

07_DTime_GateDelay_Example/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+
+component log is
+port (inp :   in std_logic;
+        C :   out std_logic);
+end component;
+signal inp_in, C_in : std_logic;
+
+begin  
+  DUT: log port map(
+     inp => inp_in,
+     C => C_in
+  );
+  inp_in <= '1', '0' after 10 ns, '1' after 20 ns;
+    
+end tb;

07_DTime_GateDelay_Example/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end