first commit

05_Fulladder_allVariants/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

05_Fulladder_allVariants/05_Fulladder_allVariants.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="fulladder_process.vhd" />
+    <File Include="fulladder_select.vhd" />
+    <File Include="fulladder_struct.vhd" />
+    <File Include="halfadder.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

05_Fulladder_allVariants/fulladder_process.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_proc is
+  port (afa_proc_i :   in std_logic;
+        bfa_proc_i :   in std_logic;
+        cinfa_proc_i :   in std_logic;
+        sumfa_proc_o : out std_logic;
+        coutfa_proc_o :  out std_logic);
+end fulladder_proc;
+
+architecture beh of fulladder_proc is
+
+signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
+signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
+
+begin
+ sig_INPUTS <= (cinfa_proc_i,bfa_proc_i,afa_proc_i); 
+
+ table : process (sig_INPUTS)
+ begin
+ IF (sig_INPUTS = "000") then sig_OUTPUTS <= "00";
+ elsif (sig_INPUTS = "001") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "010") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "011") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "100") then sig_OUTPUTS <= "01";
+ elsif (sig_INPUTS = "101") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "110") then sig_OUTPUTS <= "10";
+ elsif (sig_INPUTS = "111") then sig_OUTPUTS <= "11";
+ else sig_OUTPUTS <= "XX"; end if;
+ 
+ end process table;
+ 
+                      
+ sumfa_proc_o <= sig_OUTPUTS(0);
+ coutfa_proc_o <= sig_OUTPUTS(1);
+end beh;

05_Fulladder_allVariants/fulladder_select.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_sel is
+  port (afa_sel_i :   in std_logic;
+        bfa_sel_i :   in std_logic;
+        cinfa_sel_i :   in std_logic;
+        sumfa_sel_o : out std_logic;
+        coutfa_sel_o :  out std_logic);
+end fulladder_sel;
+
+architecture behavior of fulladder_sel is
+
+signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
+signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);
+
+begin
+ sig_INPUTS <= (cinfa_sel_i,bfa_sel_i,afa_sel_i); 
+
+ with sig_INPUTS select	
+    sig_OUTPUTS   <=  "00" when "000",	
+                      "01" when "001",
+                      "01" when "010",	
+                      "10" when "011",
+                      "01" when "100",	
+                      "10" when "101",
+                      "10" when "110",	
+                      "11" when "111",
+                      "XX" when others;
+                      
+ sumfa_sel_o <= sig_OUTPUTS(0);
+ coutfa_sel_o <= sig_OUTPUTS(1);
+end behavior;

05_Fulladder_allVariants/fulladder_struct.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity fulladder_struct is
+  port (afa_s_i :   in std_logic;
+        bfa_s_i :   in std_logic;
+        cinfa_s_i :   in std_logic;
+        sumfa_s_o : out std_logic;
+        coutfa_s_o :  out std_logic);
+end fulladder_struct;
+
+architecture structural of fulladder_struct is
+
+-- Halfadder component
+component halfadder is
+port (a_i :   in std_logic;
+      b_i :   in std_logic;
+      sum_o : out std_logic;
+      cy_o :  out std_logic);
+end component;
+
+signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;
+
+begin
+
+-- Instances of two halfadders
+  HA1: halfadder port map(
+     a_i => afa_s_i,
+     b_i => bfa_s_i,
+     sum_o => sig_ha1e,
+     cy_o => sig_ha1c);
+     
+  HA2: halfadder port map(
+  	 a_i => sig_ha1e,
+     b_i => cinfa_s_i,
+     sum_o => sumfa_s_o,
+     cy_o => sig_ha2c);
+
+-- The OR gate 
+  coutfa_s_o <= sig_ha1c OR sig_ha2c;
+     
+end structural;

05_Fulladder_allVariants/halfadder.vhd

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+-- The halfadder design
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity halfadder is
+  port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+architecture behavior of halfadder is
+begin
+  sum_o <= a_i xor b_i;
+  cy_o <= a_i and b_i;
+end behavior;

05_Fulladder_allVariants/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity testbench is
+-- empty
+end testbench;
+
+architecture tb of testbench is
+-- DUT components
+component fulladder_struct is
+  port (afa_s_i :   in std_logic;
+        bfa_s_i :   in std_logic;
+        cinfa_s_i :   in std_logic;
+        sumfa_s_o : out std_logic;
+        coutfa_s_o :  out std_logic);
+end component;
+
+component fulladder_sel is
+  port (afa_sel_i :   in std_logic;
+        bfa_sel_i :   in std_logic;
+        cinfa_sel_i :   in std_logic;
+        sumfa_sel_o : out std_logic;
+        coutfa_sel_o :  out std_logic);
+end component;
+
+component fulladder_proc is
+  port (afa_proc_i :   in std_logic;
+        bfa_proc_i :   in std_logic;
+        cinfa_proc_i :   in std_logic;
+        sumfa_proc_o : out std_logic;
+        coutfa_proc_o :  out std_logic);
+end component;
+
+
+
+signal sig_afa_s, sig_bfa_s, sig_cinfa_s, sig_sumfa_s, sig_coutfa_s: std_logic;
+signal sig_afa_sel, sig_bfa_sel, sig_cinfa_sel, sig_sumfa_sel, sig_coutfa_sel: std_logic;
+signal sig_afa_proc, sig_bfa_proc, sig_cinfa_proc, sig_sumfa_proc, sig_coutfa_proc: std_logic;
+
+begin
+
+  -- Connect DUTs
+  DUT_s: fulladder_struct port map(
+     afa_s_i => sig_afa_s,
+     bfa_s_i => sig_bfa_s,
+     cinfa_s_i => sig_cinfa_s,
+     sumfa_s_o => sig_sumfa_s,
+     coutfa_s_o => sig_coutfa_s);
+  
+   DUT_sel: fulladder_sel port map(
+     afa_sel_i => sig_afa_sel,
+     bfa_sel_i => sig_bfa_sel,
+     cinfa_sel_i => sig_cinfa_sel,
+     sumfa_sel_o => sig_sumfa_sel,
+     coutfa_sel_o => sig_coutfa_sel);
+     
+   DUT_proc: fulladder_proc port map(
+     afa_proc_i => sig_afa_proc,
+     bfa_proc_i => sig_bfa_proc,
+     cinfa_proc_i => sig_cinfa_proc,
+     sumfa_proc_o => sig_sumfa_proc,
+     coutfa_proc_o => sig_coutfa_proc);
+  
+  stim :process is
+  
+  begin
+  
+  	sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 000 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 000 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 001 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 001 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 010 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 010 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '0';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '0';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '0';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 011 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 011 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '0'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 100 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 100 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '0'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '0'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '0'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 101 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 101 NOK" severity failure;
+    
+    sig_afa_s <= '0'; sig_bfa_s <= '1'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '0'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '0'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 110 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 110 NOK" severity failure;
+    
+    sig_afa_s <= '1'; sig_bfa_s <= '1'; sig_cinfa_s <= '1';
+    sig_afa_sel <= '1'; sig_bfa_sel <= '1'; sig_cinfa_sel <= '1';
+    sig_afa_proc <= '1'; sig_bfa_proc <= '1'; sig_cinfa_proc <= '1';
+    
+    wait for 10 ns;
+    assert (sig_sumfa_s = sig_sumfa_sel) report "Test sum 111 NOK" severity failure;
+    assert (sig_coutfa_s = sig_coutfa_sel) report "Test carry 111 NOK" severity failure;
+    
+    wait;
+    
+  end process stim;
+    
+    
+    
+  
+  
+end tb;

05_Fulladder_allVariants/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+]
+[libraries.work]
+files = [
+]
+# auto-generated-end