first commit

01_Halfadder/.gitignore

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+## Default .gitignore for VHDPlus Projects
+
+## Ignore generated vhdl files, files generated by compiling with quartus
+Generated/
+incremental_db/
+output_files/
+db/
+
+## MacOS
+.DS_Store
+
+## ModelSim
+Modelsim/
+
+## Quartus specific.
+## *.qsf
+## *.qpf
+
+## ISSP
+Libraries/.qsys_edit
+
+## NIOS
+*.map
+*.objdump
+*.elf
+*.flash
+*.sopcinfo
+
+## Clangd
+.clangd/
+.cache/
+obj/
+mem_init/
+
+## BSP Libraries
+**/Software/**/generated_bsp/
+**/Software/**/compile_commands.json
+
+## Python
+*__pycache__*

01_Halfadder/01_Halfadder.vhdpproj

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+<Project>
+  <ItemGroup>
+    <File Include="design.vhd" />
+    <File Include="testbench.vhd" />
+  </ItemGroup>
+  <PropertyGroup />
+</Project>

01_Halfadder/design.vhd

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+-- Code your design here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Entity HA
+entity halfadder is
+    port (a_i :   in std_logic;
+        b_i :   in std_logic;
+        sum_o : out std_logic;
+        cy_o :  out std_logic);
+end halfadder;
+
+-- Architecture HA
+architecture behavior of halfadder is
+begin
+  -- HA is made out of 2 gates:
+    sum_o <= a_i xor b_i;
+    cy_o <= a_i and b_i;
+end behavior;

01_Halfadder/testbench.vhd

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+-- Code your testbench here
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Entity TB
+entity testbench is
+-- empty
+end testbench;
+
+
+-- Architecture TB
+architecture tb of testbench is
+
+-- DUT component declaration
+    component halfadder is
+        port (a_i :   in std_logic;
+            b_i :   in std_logic;
+            sum_o : out std_logic;
+            cy_o :  out std_logic);
+    end component;
+
+-- declare signals
+    signal sig_a, sig_b, sig_sum, sig_cy: std_logic;
+
+begin
+
+  -- DUT instantiation and port mapping
+    DUT: halfadder port map(
+        a_i => sig_a,
+        b_i => sig_b,
+        sum_o => sig_sum,
+        cy_o => sig_cy);
+    
+  -- apply testpattern
+    sig_a <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
+    sig_b <= '0', '1' after 200 ns;
+    
+end tb;

01_Halfadder/vhdl_ls.toml

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+# auto-generated
+[Libraries]
+work.files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+[libraries.work]
+files = [
+	'design.vhd',
+	'testbench.vhd'
+]
+# auto-generated-end