-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component FSM is
port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           start : in  STD_LOGIC;
           stop  : in  STD_LOGIC;
           cout  : out  STD_LOGIC_VECTOR (2 downto 0));
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_clk, sig_reset, sig_start, sig_stop : std_logic;
signal sig_cout : STD_LOGIC_VECTOR (2 downto 0);

begin  
  DUT: FSM port map(
     clk => sig_clk,
     reset => sig_reset,
     start => sig_start,
     stop => sig_stop,
     cout => sig_cout
   );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );
  


sig_start <= '0', '1' after 22 ns, '0' after 45 ns, '1' after 82 ns, '0' after 86 ns;

sig_reset <='0','1' after 102 ns, '0' after 123 ns;
sig_stop <= '0', '1' after 58 ns, '0' after 68 ns;
end tb;