40 lines
1.0 KiB
VHDL
40 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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architecture behavior of pwm is
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-- Constants for PWM parameters
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constant CLK_PERIOD : time := 20 ns; -- Assuming 50 MHz clock
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constant PWM_PERIOD : time := 10 us; -- Desired period of 10 microseconds
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constant DUTY_CYCLE : time := 7.2 us; -- 72% of the period
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-- Signal to store the counter value
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signal counter : natural range 0 to integer(PWM_PERIOD / CLK_PERIOD) - 1;
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begin
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-- Synchronous counter process
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process(CLK)
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begin
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if rising_edge(CLK) then
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if counter = integer(PWM_PERIOD / CLK_PERIOD) - 1 then
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counter <= 0;
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else
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counter <= counter + 1;
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end if;
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end if;
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end process;
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-- PWM output generation process
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process(CLK, counter)
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begin
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if rising_edge(CLK) then
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if (CLK_PERIOD * integer(counter)) < DUTY_CYCLE then
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O <= '1';
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else
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O <= '0';
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end if;
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end if;
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end process;
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end behavior; |