library IEEE;
use IEEE.std_logic_1164.all;

architecture behavior of pwm is

    -- Constants for PWM parameters
    constant CLK_PERIOD : time := 20 ns; -- Assuming 50 MHz clock
    constant PWM_PERIOD : time := 10 us;  -- Desired period of 10 microseconds
    constant DUTY_CYCLE : time := 7.2 us;  -- 72% of the period

    -- Signal to store the counter value
    signal counter : natural range 0 to integer(PWM_PERIOD / CLK_PERIOD) - 1;

begin

    -- Synchronous counter process
    process(CLK)
    begin
        if rising_edge(CLK) then
            if counter = integer(PWM_PERIOD / CLK_PERIOD) - 1 then
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    -- PWM output generation process
    process(CLK, counter)
    begin
        if rising_edge(CLK) then
            if (CLK_PERIOD * integer(counter)) < DUTY_CYCLE then
                O <= '1';
            else
                O <= '0';
            end if;
        end if;
    end process;

end behavior;