24 lines
707 B
VHDL
24 lines
707 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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architecture behavioral of counter is
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begin
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process(CLK, RST, AsyncClear)
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begin
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if AsyncClear = '1' then
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Output <= "000000"; -- Asynchrones Löschen
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elsif rising_edge(CLK) then
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if RST = '1' then
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Output <= "000000"; -- Synchroner Reset
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elsif Enable = '1' then
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if SyncLoadInput = '1' then
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Output <= Input; -- Synchrones Laden
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else
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Output <= std_logic_vector(unsigned(Output) + 1); -- Inkrement
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end if;
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end if;
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end if;
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end process;
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end behavioral; |