library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

architecture behavioral of counter is
    
begin
    process(CLK, RST, AsyncClear)
    begin
        if AsyncClear = '1' then
            Output <= "000000"; -- Asynchrones Löschen
        elsif rising_edge(CLK) then
            if RST = '1' then
                Output <= "000000"; -- Synchroner Reset
            elsif Enable = '1' then
                if SyncLoadInput = '1' then
                    Output <= Input; -- Synchrones Laden
                else
                    Output <= std_logic_vector(unsigned(Output) + 1); -- Inkrement
                end if;
            end if;
        end if;
    end process;
end behavioral;