95 lines
1.7 KiB
VHDL
95 lines
1.7 KiB
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component single_port_ram is
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port
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(
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data : in std_logic_vector(7 downto 0);
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addr : in std_logic_vector(15 downto 0);
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we : in std_logic;
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clk : in std_logic;
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q : out std_logic_vector(7 downto 0)
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);
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_clk : std_logic;
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signal sig_addr : std_logic_vector(15 downto 0);
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signal sig_q : std_logic_vector(7 downto 0);
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signal sig_data : std_logic_vector(7 downto 0);
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signal sig_we : std_logic;
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use ieee.numeric_std.all;
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begin
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DUT: single_port_ram port map(
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clk => sig_clk,
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addr => sig_addr,
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data => sig_data,
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we => sig_we,
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q => sig_q
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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stim: process
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procedure ReadRAM(read_addr : in integer) is
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begin
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sig_we <= '0';
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sig_addr <= std_logic_vector(to_unsigned(read_addr,16));
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end procedure ReadRAM;
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procedure WriteRAM(write_addr : in integer; write_data : in std_logic_vector(7 downto 0)) is
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begin
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sig_we <= '1';
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sig_addr <= std_logic_vector(to_unsigned(write_addr,16));
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sig_data <= write_data;
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end procedure WriteRAM;
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begin
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wait for 7 ns;
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WriteRAM(2,"00000001");
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wait for 20 ns;
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WriteRAM(4,"00000010");
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wait for 20 ns;
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WriteRAM(6,"00000011");
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wait for 20 ns;
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WriteRAM(8,"00000100");
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wait for 20 ns;
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WriteRAM(10,"11111111");
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wait for 30 ns;
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ReadRAM(2);
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wait for 20 ns;
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ReadRAM(4);
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wait for 20 ns;
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ReadRAM(6);
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wait for 20 ns;
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ReadRAM(8);
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wait for 20 ns;
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ReadRAM(10);
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wait for 20 ns;
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ReadRAM(11);
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wait for 20 ns;
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wait;
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end process stim;
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end tb; |