47 lines
980 B
VHDL
47 lines
980 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity single_port_ram is
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port
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(
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data : in std_logic_vector(7 downto 0);
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addr : in std_logic_vector(15 downto 0);
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we : in std_logic;
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clk : in std_logic;
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q : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture rtl of single_port_ram is
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-- Build a 2-D array type for the RAM
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subtype word_t is std_logic_vector(7 downto 0);
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type memory_t is array(2**7-1 downto 0) of word_t; -- 2**7 = 128
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signal ram : memory_t;
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-- Register to hold the address
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signal addr_reg : std_logic_vector(15 downto 0);
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begin
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process(clk)
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begin
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if(rising_edge(clk)) then
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if(we = '1') then
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ram(to_integer(unsigned(addr))) <= data;
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end if;
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-- Register the address for reading (synchron)
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addr_reg <= addr;
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end if;
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end process;
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-- asynchron data output (but attention: addr_reg changes synchronously)
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q <= ram(to_integer(unsigned(addr_reg)));
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end rtl;
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