41 lines
938 B
VHDL
41 lines
938 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity single_port_rom is
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port
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(
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addr : in std_logic_vector(3 downto 0);
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q : out std_logic_vector(4 downto 0)
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);
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end single_port_rom;
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architecture rtl of single_port_rom is
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-- Build a 2-D array type for the ROM
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subtype word_t is std_logic_vector(4 downto 0);
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type memory_t is array(0 to 15) of word_t;
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constant romdata : memory_t := (
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"10101", -- data for address 0
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"11111", -- data for address 1
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"10101",
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"11110",
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"10110",
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"10101",
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"11010",
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"10010",
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"10110",
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"11101",
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"10110",
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"10111",
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"00110",
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"11101",
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"10010",
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"10110" -- data for address 15
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);
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begin
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q <= romdata(to_integer(unsigned(addr)));
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end rtl; |