library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is
    port
    (
        addr    : in std_logic_vector(3 downto 0);
        q        : out std_logic_vector(4 downto 0)
    );
end single_port_rom;
    
architecture rtl of single_port_rom is

    -- Build a 2-D array type for the ROM
    subtype word_t is std_logic_vector(4 downto 0);
    type memory_t is array(0 to 15) of word_t;
        
    constant romdata : memory_t := (
     "10101",                            -- data for address 0
     "11111",                            -- data for address 1
     "10101",
     "11110",
     "10110",
     "10101",
     "11010",
     "10010",
     "10110",
     "11101",
     "10110",
     "10111",
     "00110",
     "11101",
     "10010",
     "10110"                             -- data for address 15
     );
          
begin
        q <= romdata(to_integer(unsigned(addr)));
        
end rtl;