81 lines
2.3 KiB
VHDL
81 lines
2.3 KiB
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity FSM is
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port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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start : in STD_LOGIC;
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stop : in STD_LOGIC;
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cout : out STD_LOGIC_VECTOR (2 downto 0));
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end FSM;
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architecture beh of FSM is
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type state_t is (cs_reset,cs_wait,cs_one,cs_two,cs_three,cs_four,cs_five);
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signal state, next_state : state_t := cs_reset;
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begin
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p_seq: process (clk,reset)
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begin
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if reset ='1' then
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state <= cs_reset;
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elsif (Clk'event and Clk ='1') then
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state <= next_state;
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end if;
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end process p_seq;
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p_comb: process (state,start,stop)
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begin
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case state is
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when cs_reset => next_state <= cs_wait;
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cout <= "XXX";
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when cs_wait => if (start='1' and stop='0') then
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next_state <= cs_one;
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else
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next_state <= cs_wait;
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end if;
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cout <= "000";
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when cs_one => if (stop='1') then
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next_state <= cs_wait;
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else
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next_state <= cs_two;
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end if;
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cout <= "001";
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when cs_two => if (stop='1') then
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next_state <= cs_wait;
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else
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next_state <= cs_three;
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end if;
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cout <= "010";
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when cs_three => if (stop='1') then
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next_state <= cs_wait;
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else
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next_state <= cs_four;
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end if;
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cout <= "011";
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when cs_four => if (stop='1') then
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next_state <= cs_wait;
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else
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next_state <= cs_five;
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end if;
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cout <= "100";
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when cs_five => next_state <= cs_wait;
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cout <= "101";
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end case;
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end process p_comb;
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end beh; |