-- Code your design here library IEEE; use IEEE.std_logic_1164.all; entity FSM is port ( clk : in STD_LOGIC; reset : in STD_LOGIC; start : in STD_LOGIC; stop : in STD_LOGIC; cout : out STD_LOGIC_VECTOR (2 downto 0)); end FSM; architecture beh of FSM is type state_t is (cs_reset,cs_wait,cs_one,cs_two,cs_three,cs_four,cs_five); signal state, next_state : state_t := cs_reset; begin p_seq: process (clk,reset) begin if reset ='1' then state <= cs_reset; elsif (Clk'event and Clk ='1') then state <= next_state; end if; end process p_seq; p_comb: process (state,start,stop) begin case state is when cs_reset => next_state <= cs_wait; cout <= "XXX"; when cs_wait => if (start='1' and stop='0') then next_state <= cs_one; else next_state <= cs_wait; end if; cout <= "000"; when cs_one => if (stop='1') then next_state <= cs_wait; else next_state <= cs_two; end if; cout <= "001"; when cs_two => if (stop='1') then next_state <= cs_wait; else next_state <= cs_three; end if; cout <= "010"; when cs_three => if (stop='1') then next_state <= cs_wait; else next_state <= cs_four; end if; cout <= "011"; when cs_four => if (stop='1') then next_state <= cs_wait; else next_state <= cs_five; end if; cout <= "100"; when cs_five => next_state <= cs_wait; cout <= "101"; end case; end process p_comb; end beh;