109 lines
1.8 KiB
VHDL
109 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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--use IEEE.std_artih.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component MyDesign is
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port (clk_i : in std_logic;
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data_i : in std_logic);
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end component;
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signal sig_data, sig_clk: std_logic;
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signal send_count : integer :=0;
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begin
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-- Connect DUT with tb signals
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DUT: MyDesign port map(
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clk_i => sig_clk,
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data_i => sig_data);
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stimTest : process
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procedure send(d0,d1,d2,d3 : in std_logic) is
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begin
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if (send_count=0) then
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assert ((d0='1') AND (d1='1') AND (d2='1') AND (d3='1')) report "error in first frame (d0,d1,d2,d3) is "
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& std_logic'image(d0)
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& std_logic'image(d1)
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& std_logic'image(d2)
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& std_logic'image(d3)
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severity error;
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end if;
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wait for 4 ms;
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sig_data <= '0';
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sig_clk <= '1';
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for I in 0 to 3 loop
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wait for 1 ms;
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sig_clk <= NOT sig_clk;
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end loop;
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sig_data <= d0;
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sig_clk <= '1';
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wait for 1 ms;
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sig_clk <= '0';
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wait for 1 ms;
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sig_data <= d1;
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sig_clk <= '1';
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wait for 1 ms;
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sig_clk <= '0';
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wait for 1 ms;
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sig_data <= d2;
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sig_clk <= '1';
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wait for 1 ms;
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sig_clk <= '0';
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wait for 1 ms;
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sig_data <= d3;
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sig_clk <= '1';
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wait for 1 ms;
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sig_clk <= '0';
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wait for 1 ms;
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sig_data <= '0';
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sig_clk <= '1';
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wait for 1 ms;
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sig_clk <= '0';
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wait for 1 ms;
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sig_data <= '1';
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sig_clk <= '1';
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wait for 1ms;
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sig_clk <= '0';
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send_count <= send_count+1;
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end procedure send;
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begin
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sig_clk <= '0';
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sig_data <= '1';
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send('1','0','1','0');
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wait for 10 ms;
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send('0','1','0','1');
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wait;
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end process stimTest;
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end tb;
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