library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_artih.all;


entity testbench is
end testbench; 


architecture tb of testbench is

component MyDesign is
port (clk_i :   in std_logic;
      data_i :   in std_logic);
end component;



signal sig_data, sig_clk: std_logic;
signal send_count : integer :=0;

begin

  -- Connect DUT with tb signals
  DUT: MyDesign port map(
     clk_i => sig_clk,
     data_i => sig_data);
     
  stimTest : process
  
   procedure send(d0,d1,d2,d3 : in std_logic) is
    begin
    
    if (send_count=0) then
      assert ((d0='1') AND (d1='1') AND (d2='1') AND (d3='1')) report "error in first frame (d0,d1,d2,d3) is " 
      & std_logic'image(d0)
      & std_logic'image(d1)
      & std_logic'image(d2)
      & std_logic'image(d3)
      severity error; 
    end if;
    
    wait for 4 ms;
    
    sig_data <= '0';
    sig_clk <= '1';
    
    for I in 0 to 3 loop
		wait for 1 ms;
        sig_clk <= NOT sig_clk;
	end loop;
    
    sig_data <= d0;
    sig_clk <= '1';
    wait for 1 ms;
    sig_clk <= '0';
    wait for 1 ms;
    
    sig_data <= d1;
    sig_clk <= '1';
    wait for 1 ms;
    sig_clk <= '0';
    wait for 1 ms;
    
    sig_data <= d2;
    sig_clk <= '1';
    wait for 1 ms;
    sig_clk <= '0';
    wait for 1 ms;
    
    sig_data <= d3;
    sig_clk <= '1';
    wait for 1 ms;
    sig_clk <= '0';
    wait for 1 ms;
    
    sig_data <= '0';
    sig_clk <= '1';
    wait for 1 ms;
    sig_clk <= '0';
    wait for 1 ms;
    
    sig_data <= '1';
    sig_clk <= '1';
    wait for 1ms;
    sig_clk <= '0';
    
    send_count <= send_count+1;

   end procedure send;
   
   
  begin
  
  sig_clk <= '0';
  sig_data <= '1';
  
  send('1','0','1','0');
  
  wait for 10 ms;
  
  send('0','1','0','1');
  
   
  wait;
  end process stimTest;

end tb;