41 lines
983 B
VHDL
41 lines
983 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component minArith is
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port (a_i : in std_logic_vector (7 downto 0);
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b_i : in std_logic_vector (7 downto 0);
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ssum_o : out std_logic_vector (7 downto 0);
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sdiff_o : out std_logic_vector (7 downto 0);
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usum_o : out std_logic_vector (7 downto 0);
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udiff_o : out std_logic_vector (7 downto 0);
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ainc_o : out std_logic_vector (7 downto 0));
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end component;
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signal sig_a, sig_b, sig_ssum, sig_sdiff, sig_usum, sig_udiff, sig_ainc : std_logic_vector(7 downto 0);
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begin
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DUT: minArith port map(
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a_i => sig_a,
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b_i => sig_b,
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ssum_o => sig_ssum,
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sdiff_o => sig_sdiff,
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usum_o => sig_usum,
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udiff_o => sig_udiff,
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ainc_o => sig_ainc );
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sig_a <= "00000001", "00000010" after 100 ns, "00001010" after 200 ns;
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sig_b <= "00000001", "00000011" after 100 ns, "00100010" after 200 ns;
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end tb;
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