library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench; 


architecture tb of testbench is

component minArith is
port (a_i :   in std_logic_vector (7 downto 0);
      b_i :   in std_logic_vector (7 downto 0);
      ssum_o : out std_logic_vector (7 downto 0);
      sdiff_o :  out std_logic_vector (7 downto 0);
      usum_o : out std_logic_vector (7 downto 0);
      udiff_o :  out std_logic_vector (7 downto 0);
      ainc_o :  out std_logic_vector (7 downto 0));
end component;


signal sig_a, sig_b, sig_ssum, sig_sdiff, sig_usum, sig_udiff, sig_ainc : std_logic_vector(7 downto 0);

begin

  DUT: minArith port map(
      a_i => sig_a,
      b_i => sig_b,
      ssum_o => sig_ssum,
      sdiff_o => sig_sdiff,
      usum_o => sig_usum,
      udiff_o => sig_udiff,
      ainc_o => sig_ainc );

  
  
  sig_a <= "00000001", "00000010" after 100 ns, "00001010" after 200 ns;
  sig_b <= "00000001", "00000011" after 100 ns, "00100010" after 200 ns;

end tb;