60 lines
925 B
VHDL
60 lines
925 B
VHDL
-- Code your testbench here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity testbench is
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end testbench;
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architecture tb of testbench is
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component myDFF is
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port ( clk:in std_logic;
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D:in std_logic;
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reset:in std_logic;
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Q:out std_logic);
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end component;
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component clkGen is
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port (clk : out std_logic);
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end component;
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signal sig_D, sig_clk, sig_Q, sig_reset : std_logic;
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begin
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DUT: myDFF port map(
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clk => sig_clk,
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D => sig_D,
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reset => sig_reset,
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Q => sig_Q
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);
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mClkGen : clkGen port map(
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clk => sig_clk
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);
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res_stim : process
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begin
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sig_reset <= '0';
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wait for 2 ns;
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sig_reset <= '1';
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wait for 10 ns;
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sig_reset <= '0';
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wait for 20 ns;
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sig_reset <= '1';
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wait for 1 ns;
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sig_reset <= '0';
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wait;
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end process res_stim;
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d_stim : process
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begin
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sig_D <= '0';
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wait for 17 ns;
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sig_D <= '1';
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wait for 30 ns;
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sig_D <= '0';
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wait;
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end process d_stim;
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end tb; |