-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component myDFF is
port ( clk:in std_logic;
       D:in std_logic;
       reset:in std_logic;
       Q:out std_logic);
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_D, sig_clk, sig_Q, sig_reset : std_logic;

begin  
  DUT: myDFF port map(
     clk => sig_clk,
     D => sig_D,
     reset => sig_reset,
     Q => sig_Q
  );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );
  
res_stim : process 
begin 
 sig_reset <= '0';
 wait for 2 ns;
 sig_reset <= '1';
 wait for 10 ns;
 sig_reset <= '0';
 wait for 20 ns;
 sig_reset <= '1';
 wait for 1 ns;
 sig_reset <= '0';
 wait;
end process res_stim;

d_stim : process
begin
 sig_D <= '0';
 wait for 17 ns;
 sig_D <= '1';
 wait for 30 ns;
 sig_D <= '0';
 wait;
end process d_stim;

end tb;