24 lines
383 B
VHDL
24 lines
383 B
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity myDFF is
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port ( clk:in std_logic;
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D:in std_logic;
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reset:in std_logic;
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Q:out std_logic);
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end myDFF;
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architecture beh of myDFF is
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begin
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DFF: process ( Clk, reset )
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begin
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If reset ='1' then
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Q <='0';
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Elsif (Clk'event and Clk ='1') then
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Q <= D ;
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end if ;
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end process DFF;
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end beh; |