-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity myDFF is 
port ( clk:in std_logic;
       D:in std_logic;
       reset:in std_logic;
       Q:out std_logic);
end myDFF;

architecture beh of myDFF is
begin

DFF: process ( Clk, reset )
begin
 If reset ='1' then
  Q <='0';
 Elsif (Clk'event and Clk ='1') then
  Q <= D ;
 end if ;
end process DFF;

end beh;