21 lines
300 B
VHDL
21 lines
300 B
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity InfLatch is
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port ( D:in std_logic;
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En:in std_logic;
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Q:out std_logic);
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end InfLatch;
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architecture beh of InfLatch is
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begin
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p0: process (D,En)
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begin
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if En= '1' then
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Q <= D;
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end if;
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end process p0;
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end beh; |