-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity InfLatch is 
port ( D:in std_logic;
       En:in std_logic;
       Q:out std_logic);
end InfLatch;

architecture beh of InfLatch is
begin

p0: process (D,En)
begin
 if En= '1' then
 Q <= D;
 end if;
end process p0;

end beh;