18 lines
314 B
VHDL
18 lines
314 B
VHDL
-- Code your design here
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity log is
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port (inp : in std_logic;
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C : out std_logic);
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end log;
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architecture behavior of log is
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signal A,B : std_logic;
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begin
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A <= NOT inp after 1 ns;
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B <= A NAND '1' after 1 ns;
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C <= A AND B after 1 ns;
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end behavior;
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