-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;


entity log is
  port (inp :   in std_logic;
        C :   out std_logic);
end log;

architecture behavior of log is
signal A,B : std_logic;
begin
  A <= NOT inp after 1 ns;
  B <= A NAND '1' after 1 ns;
  C <= A AND B after 1 ns;
end behavior;